EP3SL200H780C4LN vs EP3SL200H780I4L 比較

詳細並排比較 EP3SL200H780C4LN 由 Altera 與 EP3SL200H780I4L 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Altera
EP3SL200H780C4LN EP3SL200H780C4LN - Stratix III L 200K Logic Element FPGA | Intel

EP3SL200H780C4LN - Stratix III L 200K Logic Element FPGA | Intel

EP3SL200H780C4LN ⚠ 最後購買機會

規格比較

參數 EP3SL200H780C4LN EP3SL200H780I4L
品牌 Altera Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 最後購買 NRND
Series Stratix III L —
Logic Elements 200,000 200,000
Logic Array Blocks (LABs) 8,000 8,000
User I/Os 488 —
Total Memory Bits 10,901,504 —
腳位數 780 —
封裝 780-BBGA / HBGA / FCBGA 780-pin FC-HFBGA (Flip-Chip)
安裝類型 Surface Mount Surface Mount
Core Supply Voltage 0.86 V to 1.15 V 0.86 V to 1.15 V
工作溫度 0 C to +70 C (commercial, 'C' grade) -40C to +100C (Industrial)
Speed Grade 4 (commercial, slowest of grade 4) I4 (Industrial)
Transceivers Multi-quad, up to 6.375 Gbps Up to 24 channels
DSP Blocks (18x18 multipliers) [DATA_NEEDED: exact multiplier count] —
PLLs 8 —
Configuration JTAG / Passive Serial / Fast Passive Parallel —
RoHS 狀態 Compliant Compliant
Lead-Free Yes —
Family — Stratix III L
Embedded Memory (Bits) — 10,901,504
Maximum User I/O — 488
Process Technology — 65 nm CMOS
Internal Performance — 375 MHz
Transceiver Data Rate — Up to 6.375 Gbps
DSP Blocks — 9x9 / 18x18 / 36x36 multipliers
Memory Interface Support — DDR3, DDR2, DDR, QDR II+, RLDRAM II
JTAG Support — IEEE Std 1149.1 Boundary-Scan
HardCopy Support — Compatible (Lattice-style migration path via HardCopy III)

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