EP3SL50F484I4LG vs EP3SL50F484I3N 比較
詳細並排比較 EP3SL50F484I4LG 由 Intel 與 EP3SL50F484I3N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Intel
EP3SL50F484I4LG - Stratix III L FPGA, 47.5K LE, 484-FCBGA | Altera (Intel)
EP3SL50F484I4LG Nrnd規格比較
| 參數 | EP3SL50F484I4LG | EP3SL50F484I3N |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | 最後購買 |
| Family | Stratix III L | Stratix III L |
| Series | EP3SL50 | — |
| Logic Elements | 47,500 | 47,500 |
| Embedded Memory | 2,184,192 bits (273 KB) | 2,184,192 bits (2.1 Mbit) |
| User I/Os | 296 | — |
| 封裝 | 484-Ball FCBGA (FBGA) | 484-ball FBGA (FC-FBGA, 23x23 mm, 1.0 mm pitch) |
| 安裝類型 | Surface Mount | Surface Mount (SMT) |
| 工作溫度 | -40C to +100C (Industrial) | — |
| Speed Grade | I4 (fast) | — |
| 供應電壓 | 0.85 V / 1.1 V / 1.2 V / 2.5 V / 3.3 V (multi-rail) | — |
| Process Node | 40 nm | — |
| RoHS 狀態 | Compliant | — |
| Lead-Free | Yes | — |
| Total I/O Banks | [DATA_NEEDED: I/O bank count] | — |
| DSP Blocks | [DATA_NEEDED: DSP block count] | — |
| Transceivers | [DATA_NEEDED: transceiver channel count] | — |
| Configuration Memory | SRAM-based | — |
| Configuration Interface | JTAG / Passive Serial / Fast Passive Parallel | — |
| Logic Array Blocks (LABs) | — | 1,900 |
| Embedded 18x18 Multipliers | — | 218 |
| Maximum User I/O | — | 296 |
| Process Technology | — | 65 nm CMOS |
| Core Voltage | — | 0.9 V / 1.1 V |
| Maximum Core Frequency | — | 500 MHz |
| 工作接面溫度 | — | -40C to +100C (Industrial) |
| Lead-Free / RoHS | — | Lead Free / Compliant |
| MSL 等級 | — | [DATA_NEEDED: MSL level per JEDEC J-STD-020] |
| Programming Tool | — | Quartus II (legacy) |