EP610DC-15 vs EP610DI-25 比較
詳細並排比較 EP610DC-15 由 Altera 與 EP610DI-25 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610DC-15 | EP610DI-25 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Product Family | Classic EPLD (EP610) | — |
| Architecture | UV-erasable CMOS PAL-type | — |
| Macrocells | 16 | 16 |
| Logic Expanders | 4 | — |
| Dedicated Inputs | 20 | 4 |
| Bidirectional I/O Pins | 16 | — |
| Total Product Terms | 160 | — |
| Propagation Delay (tPD) | 15 ns (speed grade -15) | 25 ns |
| Maximum Internal Clock Frequency | 71.4 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V nominal |
| 工作溫度 | 0C to 70C (commercial) | Industrial (per "I" suffix) |
| 封裝 | 24-pin Ceramic DIP (CDIP-24) with UV window | — |
| 安裝類型 | Through-Hole | Through-Hole (DIP) |
| Programming Method | JEDEC fuse map, UV erasure | — |
| Technology | CMOS | CMOS EPROM (UV-erasable) |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | — |
| Part Family | — | Classic EPLD |
| Maximum Pipelined Clock Frequency | — | 100 MHz (max fCNT, per family datasheet) |
| I/O Pins | — | 16 (bidirectional) |
| Total User I/O | — | 20 |
| Package Type | — | Ceramic DIP, glass-sealed (windowed), R-GDIP-T24 |
| 腳位數 | — | 24 |
| Speed Grade Suffix | — | 25 = 25 ns |
| Compliance | — | RoHS status unknown (legacy 1990s part) |