EP610DC-35 vs EP610DC-20 比較
詳細並排比較 EP610DC-35 由 Altera 與 EP610DC-20 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610DC-35 | EP610DC-20 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Device Type | CPLD - Classic EPLD | — |
| Family | Altera Classic EP610 | Classic EP610 |
| Macrocells | 16 | — |
| Usable Gates | 300 | — |
| Propagation Delay (tPD) | 35 ns | 22 ns |
| Maximum Frequency (fMAX) | 28.6 MHz | — |
| Pipelined Data Rate | up to 100 MHz | — |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V (5 V nominal) |
| Process Technology | CMOS | CMOS, UV-erasable floating gate |
| Program/erase Method | UV-erasable (windowed CERDIP) | — |
| 封裝 | 24-pin CDIP (windowed CERDIP) 0.300 inch | 24-pin Ceramic DIP (CDIP-24) with UV window |
| 安裝類型 | Through-Hole (DIP) | Through-hole |
| 工作溫度 | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] | 0 °C to 70 °C (commercial) |
| Manufacturer | Originally Altera; today supplied via Rochester Electronics (authorized) | — |
| RoHS 狀態 | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] | [DATA_NEEDED: RoHS compliance status] |
| Product Type | — | CMOS UV-Erasable Programmable Logic Device (EPLD) |
| Logic Macrocells | — | 16 |
| Dedicated Inputs | — | 4 |
| I/O Pins | — | 16 (bidirectional) |
| Total Usable Pins | — | 20 |
| Product Terms (p-terms) | — | 160 |
| Maximum Toggle Frequency (fMAX) | — | 55.6 MHz |
| Programming Method | — | UV erasure + parallel programmer |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |