EP610DI-30 vs EP610DC-35 比較
詳細並排比較 EP610DI-30 由 Rochester Electronics 與 EP610DC-35 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Rochester Electronics
EP610DI-30 - 16-Macrocell Classic EPLD, 30ns, CERDIP-24 | Rochester Electronics
EP610DI-30 ✓ 啟用中
規格比較
| 參數 | EP610DI-30 | EP610DC-35 |
|---|---|---|
| 品牌 | Rochester Electronics | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | NRND |
| Device Type | EPLD (Erasable Programmable Logic Device) | CPLD - Classic EPLD |
| Family | Classic EP610 | Altera Classic EP610 |
| Macrocells | 16 | 16 |
| Propagation Delay (tPD) | 30 ns | 35 ns |
| Pipelined Data Rate | 100 MHz | up to 100 MHz |
| Technology | CMOS | — |
| 供應電壓 | 5 V (single supply) | — |
| 封裝 | CERDIP-24 (windowed, UV-erasable) | 24-pin CDIP (windowed CERDIP) 0.300 inch |
| 安裝類型 | Through-Hole | Through-Hole (DIP) |
| Programmable Elements | EPROM (UV-erasable, windowed) | — |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] |
| I/O Pins | [DATA_NEEDED: I/O pin count] | — |
| Logic Capacity | [DATA_NEEDED: usable gates / logic capacity] | — |
| RoHS 狀態 | unknown | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] |
| Lead-Free | unknown | — |
| Original Manufacturer | Altera (now Intel) | — |
| Current Supplier | Rochester Electronics (authorized continuing source) | — |
| MSL 等級 | N/A (through-hole, non-surface-mount) | — |
| Usable Gates | — | 300 |
| Maximum Frequency (fMAX) | — | 28.6 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Process Technology | — | CMOS |
| Program/erase Method | — | UV-erasable (windowed CERDIP) |
| Manufacturer | — | Originally Altera; today supplied via Rochester Electronics (authorized) |