EP610IDC-15 vs EP610DI-30 比較
詳細並排比較 EP610IDC-15 由 Intel 與 EP610DI-30 由 Rochester Electronics. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Rochester Electronics
EP610DI-30 - 16-Macrocell Classic EPLD, 30ns, CERDIP-24 | Rochester Electronics
EP610DI-30 ✓ 啟用中規格比較
| 參數 | EP610IDC-15 | EP610DI-30 |
|---|---|---|
| 品牌 | Intel | Rochester Electronics |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | 啟用中 |
| Device Family | Altera Classic EPLD | — |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | — |
| Propagation Delay (tPD) | 15 ns | 30 ns |
| Maximum Frequency | 66 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| 工作溫度 | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| Process Technology | CMOS, UV-erasable / OTP | — |
| 封裝 | 24-pin CerDIP (ceramic DIP) | CERDIP-24 (windowed, UV-erasable) |
| 安裝類型 | Through-hole | Through-Hole |
| I/O Pins | 24 (per package; macrocell-programmable) | [DATA_NEEDED: I/O pin count] |
| Logic-Block Architecture | AND/OR macrocell array with programmable flip-flops | — |
| Program/Erase | UV-erasable, OTP-compatible | — |
| Development Tool | MAX+PLUS II | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status of CerDIP variant] | unknown |
| Programming Current | 11.0 mA typical (per Classic family datasheet) | — |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Family | — | Classic EP610 |
| Pipelined Data Rate | — | 100 MHz |
| Technology | — | CMOS |
| 供應電壓 | — | 5 V (single supply) |
| Programmable Elements | — | EPROM (UV-erasable, windowed) |
| Logic Capacity | — | [DATA_NEEDED: usable gates / logic capacity] |
| Lead-Free | — | unknown |
| Original Manufacturer | — | Altera (now Intel) |
| Current Supplier | — | Rochester Electronics (authorized continuing source) |
| MSL 等級 | — | N/A (through-hole, non-surface-mount) |