EP610ILC-10 vs EP610JI-30 比較
詳細並排比較 EP610ILC-10 由 Altera 與 EP610JI-30 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610ILC-10 | EP610JI-30 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Device Family | Classic EPLD | — |
| Product Type | UV-Erasable / OTP PLD | — |
| Architecture | PAL-type with macrocells | — |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | — |
| Product Terms | 160 | 160 |
| I/O Pins | 16 | 16 |
| Dedicated Inputs | 4 | 4 |
| 供應電壓 | 5 V (single supply) | 5 V (single supply) |
| Pin-to-Pin Delay (tPD) | 10 ns (grade -10) | — |
| Counter Frequency (fCNT) | 100 MHz | — |
| Logic Family Compatibility | TTL (5 V CMOS/TTL-compatible I/O) | — |
| 封裝 | PLCC-28 (plastic J-lead chip carrier) | CQCC28 (windowed ceramic JLCC, J-bend) |
| 安裝類型 | Surface Mount (PLCC socket or solder) | Surface Mount (JLCC) |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | -40C to +85C (industrial, per EP610 family suffix convention) |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status - vintage ceramic package, likely non-RoHS] |
| Family | — | Altera Classic EPLD (EP610) |
| Device Type | — | UV Erasable Programmable Logic Device (EPLD) |
| Propagation Delay (tpd) | — | 30 ns (max) |
| Pipelined Data Rate | — | Up to 100 MHz |
| External Clocks | — | 2 |
| Process Technology | — | CMOS |
| Package Code | — | JLCC-28 / CQCC28 |
| Erasure Method | — | Ultraviolet (UV) via top window |
| Programming | — | Altera Logic Programmer compatible |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |