EP610ILC10 vs EP610ILC-10 比較
詳細並排比較 EP610ILC10 由 Intel 與 EP610ILC-10 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610ILC10 | EP610ILC-10 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | Classic EPLD (EP610) | — |
| Logic Elements | 16 macrocells | — |
| Gates | 300 gates equivalent | — |
| Product Terms | 160 | 160 |
| I/O Lines | 16 | — |
| Dedicated Inputs | 4 | 4 |
| Propagation Delay (tPD) | 15 ns (10 ns speed grade) | — |
| Maximum Internal Frequency | 100 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| 工作溫度 | -40 C to +85 C (Industrial) | [DATA_NEEDED: operating temperature range] |
| Technology | CMOS, UV-erasable / OTP | — |
| Architecture | PAL-type AND-OR-NOT | PAL-type with macrocells |
| 封裝 | 28-pin PLCC (J-Lead) | PLCC-28 (plastic J-lead chip carrier) |
| 安裝類型 | Surface Mount / Socket | Surface Mount (PLCC socket or solder) |
| RoHS 狀態 | Unknown - verify with manufacturer | [DATA_NEEDED: RoHS compliance] |
| Device Family | — | Classic EPLD |
| Product Type | — | UV-Erasable / OTP PLD |
| Macrocells | — | 16 |
| Usable Gates | — | 300 |
| I/O Pins | — | 16 |
| 供應電壓 | — | 5 V (single supply) |
| Pin-to-Pin Delay (tPD) | — | 10 ns (grade -10) |
| Counter Frequency (fCNT) | — | 100 MHz |
| Logic Family Compatibility | — | TTL (5 V CMOS/TTL-compatible I/O) |