EP610IPC-25 vs EP610LC-15 比較
詳細並排比較 EP610IPC-25 由 Intel 與 EP610LC-15 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610IPC-25 | EP610LC-15 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | Classic EPLD (EP610) | Altera Classic EPLD (EP610) |
| Architecture | PAL-type, CMOS, Erasable | — |
| Propagation Delay (tpd) | 25 ns (max) | 15 ns |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Maximum Inputs | 20 | — |
| Maximum I/O Pins | 16 | — |
| Dedicated Outputs | 16 | — |
| Product Terms | 160 | — |
| 工作溫度 | 0 °C to +70 °C (Commercial) | 0C to +70C (commercial) [DATA_NEEDED: full temperature grade] |
| 封裝 | 24-pin PDIP (Plastic DIP) | 28-pin PLCC (J-lead, plastic OTP) |
| Technology | CMOS, UV-erasable (windowless in IPC pkg) | — |
| TTL Compatibility | 100% TTL emulation | — |
| 安裝類型 | Through-Hole | Surface Mount |
| MSL 等級 | [DATA_NEEDED: MSL level] | [DATA_NEEDED: MSL rating] |
| RoHS 狀態 | Non-compliant (contains Pb, PDIP package) | unknown |
| Logic Capacity | Equivalent to ~24 standard 24-pin PALs | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Logic Elements / Macrocells | — | 16 macrocells |
| Equivalent Gates | — | 300 gates |
| Counter Frequency (fmax) | — | 83.3 MHz |
| Pipelined Data Rate | — | up to 100 MHz |
| Supply Voltage (Vcc) | — | 5 V (single supply) |
| Process Technology | — | CMOS |
| 腳位數 | — | 28 |
| Programming | — | OTP (one-time programmable) |