EP610LC15 vs EP610DC-15 比較
詳細並排比較 EP610LC15 由 Rochester Electronics 與 EP610DC-15 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Rochester Electronics
EP610LC15 - 16-Macrocell Classic EPLD, 15ns, 5V, PLCC-28 | Rochester
EP610LC15 Obsolete
規格比較
| 參數 | EP610LC15 | EP610DC-15 |
|---|---|---|
| 品牌 | Rochester Electronics | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Family | Classic EPLD (EP610) | — |
| Number of Macrocells | 16 | — |
| Number of Usable Gates | [DATA_NEEDED: usable gate count] | — |
| Propagation Delay (tPD) | 15 ns | 15 ns (speed grade -15) |
| Maximum Toggle Frequency (fMAX) | 83.3 MHz | — |
| Supply Voltage (VCC) | 5 V (±10%) | 4.75 V to 5.25 V |
| Dedicated Inputs | 10 | 20 |
| I/O Pins | 16 | — |
| Total Logic Pins | 24 | — |
| Technology | UV-erasable EPROM, CMOS | CMOS |
| 封裝 | PLCC-28 (J-Lead) | 24-pin Ceramic DIP (CDIP-24) with UV window |
| 工作溫度 | 0 °C to +70 °C (LC suffix = commercial) | 0C to 70C (commercial) |
| Programming Interface | Altera 4-pin serial (Classic algorithm) | — |
| Security Bit | Yes (programmable) | — |
| RoHS 狀態 | Compliant (Rochester re-creation) | [DATA_NEEDED: RoHS status] |
| Product Family | — | Classic EPLD (EP610) |
| Architecture | — | UV-erasable CMOS PAL-type |
| Macrocells | — | 16 |
| Logic Expanders | — | 4 |
| Bidirectional I/O Pins | — | 16 |
| Total Product Terms | — | 160 |
| Maximum Internal Clock Frequency | — | 71.4 MHz |
| 安裝類型 | — | Through-Hole |
| Programming Method | — | JEDEC fuse map, UV erasure |