EP610LI-15 vs EP610LC-15 比較

詳細並排比較 EP610LI-15 由 Altera 與 EP610LC-15 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP610LI-15 EP610LC-15
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 最後購買 Obsolete
Device Family Classic EPLD EP610 —
Macrocells 16 —
Propagation Delay (tPD) 15 ns —
Counter Frequency (fCNT) 83.3 MHz —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) —
工作溫度 0 C to +70 C (commercial, "I" grade) 0C to +70C (commercial) [DATA_NEEDED: full temperature grade]
Process Technology CMOS EPROM (UV-erasable) CMOS
封裝 24-pin ceramic DIP, side-brazed, windowed (DIP-24) 28-pin PLCC (J-lead, plastic OTP)
腳位數 24 —
Programming Method UV erase + EPROM programmer —
Logic Blocks AND/OR array, 16 output macrocells —
I/O Standard TTL/CMOS compatible —
輸出類型 3-state —
RoHS 狀態 Non-compliant (ceramic DIP, SnPb finish typical) unknown
Manufacturer (current) Rochester Electronics (authorized Altera legacy distributor) —
MSL 等級 [DATA_NEEDED: MSL level] [DATA_NEEDED: MSL rating]
Product Type — Classic EPLD (Erasable Programmable Logic Device)
Family — Altera Classic EPLD (EP610)
Logic Elements / Macrocells — 16 macrocells
Equivalent Gates — 300 gates
Propagation Delay (tpd) — 15 ns
Counter Frequency (fmax) — 83.3 MHz
Pipelined Data Rate — up to 100 MHz
Supply Voltage (Vcc) — 5 V (single supply)
安裝類型 — Surface Mount
腳位數 — 28
Programming — OTP (one-time programmable)

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