EP610PC-35 vs EP610PC-20 比較
詳細並排比較 EP610PC-35 由 Rochester Electronics 與 EP610PC-20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610PC-35 | EP610PC-20 |
|---|---|---|
| 品牌 | Rochester Electronics | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | Obsolete |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Classic EPLD | Classic EPLD |
| Macrocells | 16 | — |
| Usable Gates | 300 | 300 |
| Propagation Delay (tPD) | 37 ns (max, -35 speed grade) | 20 ns |
| Internal Counter Frequency | up to 100 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V ±10% |
| Supply Voltage - Internal | 4.75 V to 5.25 V | — |
| 工作溫度 | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Programmable Type | EPLD (UV-erasable window variant: EP610DC; plastic OTP) | — |
| 封裝 | 24-pin PDIP (Plastic DIP, 0.600" wide, through-hole) | PDIP-24 |
| 安裝類型 | Through Hole | — |
| Supplier Device Package | 24-PDIP | — |
| Logic Family | CMOS | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status - not confirmed in provided data] | Non-compliant (legacy PDIP) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| MSL 等級 | [DATA_NEEDED: MSL level] | — |
| Logic Elements | — | 16 macrocells |
| Maximum Operating Frequency | — | 100 MHz (pipelined) |
| 腳位數 | — | 24 |
| Process Technology | — | CMOS EPROM |
| Programmable Flip-Flops | — | 16 |
| Input Pins | — | 24 |
| Output Pins | — | 16 |
| I/O Compatibility | — | TTL |
| Program/Erase Method | — | UV (windowed) or OTP |