EP610PC30 vs EP610PC-15 比較
詳細並排比較 EP610PC30 由 Altera 與 EP610PC-15 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610PC30 | EP610PC-15 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | NRND |
| Device Type | EPLD (Erasable Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Family | Classic EP610 | Classic EPLD |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | 300 gates |
| Propagation Delay (tPD) | 30 ns | — |
| Maximum Toggle Frequency | 33.3 MHz | — |
| Pipelined Data Rate | Up to 100 MHz | Up to 100 MHz |
| Supply Voltage (VCC) | 5 V | 5 V (single supply) |
| Technology | CMOS | CMOS |
| 封裝 | PDIP-24 | PDIP-24 (plastic DIP, 24-pin) |
| 安裝類型 | Through-Hole | Through-Hole (DIP) |
| Programming | EPROM/EEPROM-based, MAX+plus II toolchain | — |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| RoHS 狀態 | Not applicable (legacy through-hole, contains Pb per historical datasheet) | [DATA_NEEDED: RoHS status] |
| Logic Capacity | 16 macrocells / 300 gates equivalent | — |
| Configuration Memory | Non-volatile (UV-erasable or OTP variant) | — |
| Manufacturer (Original) | Altera Corporation (now Intel FPGA) | — |
| Current Distributor | Rochester Electronics, LLC | — |
| Logic Delay (tPD) | — | 15 ns (pin-to-pin, -15 speed grade) |
| Maximum Counter Frequency | — | 100 MHz (per family datasheet) |
| Architecture | — | PAL-type, sum-of-products AND/OR array |
| TTL Emulation | — | 100% TTL compatible |
| 腳位數 | — | 24 pins |
| Development Tool | — | Altera MAX+PLUS II |
| Logic Test Circuitry | — | On-board for AC/DC verification |