EP910DI-30 vs EP9100C-30 比較
詳細並排比較 EP910DI-30 由 Rochester Electronics 與 EP9100C-30 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Rochester Electronics
EP910DI-30 - 24-Macrocell EPLD, 30ns, CDIP-40 | Altera (Rochester)
EP910DI-30 Nrnd
規格比較
| 參數 | EP910DI-30 | EP9100C-30 |
|---|---|---|
| 品牌 | Rochester Electronics | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Product Type | UV-Erasable Programmable Logic Device (EPLD) | — |
| Family | Classic EPLD (Altera EP910 series) | Altera Classic EPLD |
| Macrocell Count | 24 | — |
| Propagation Delay (tpd) | 30 ns | — |
| Maximum Toggle Frequency (fmax) | 62 MHz | — |
| Supply Voltage (VCC) | 5 V (single supply) | 4.75 V to 5.25 V (5 V nominal) |
| Technology | CMOS, UV-erasable EPROM | CMOS, UV-erasable (window) or OTP |
| 封裝 | CDIP-40 (ceramic DIP, 40-pin with UV window) | 40-pin ceramic DIP (CDIP) / 44-pin PLCC (windowed) / 40-pin PDIP |
| 安裝類型 | Through-Hole (DIP) | Through-Hole (DIP) / Surface Mount (PLCC) |
| Dedicated Inputs | 10 | 24 |
| Dedicated I/O Pins | 12 (12 input + 12 output) | — |
| Output Enable Pins | 2 | — |
| 腳位數 | 40 | — |
| Programmable Logic Element | JEDEC fuse map (3rd-party programmer) | — |
| 工作溫度 | -40C to +85C (industrial) | 0C to +70C (commercial) |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: rohs_status] |
| Manufacturer (Original) | Altera (now Intel PSG) | — |
| Current Distributor / Authorized Aftermarket | Rochester Electronics, LLC | — |
| Logic Density | — | 900 usable gates (approx.) |
| Macrocells | — | 48 |
| Flip-Flops | — | 24 |
| Propagation Delay (tPD) | — | 30 ns |
| Maximum Toggle Frequency (fMAX) | — | 62.5 MHz |
| I/O Standard | — | TTL-compatible |
| Programming Method | — | JEDEC via Altera APU or compatible programmer |
| Military Grade Variant | — | EP9100C-30/883 (MIL-STD-883 compliant) |