EP910ILC-12 vs EP910ILC-25 比較
詳細並排比較 EP910ILC-12 由 Intel 與 EP910ILC-25 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910ILC-12 | EP910ILC-25 |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera EP910 Classic EPLD | EP910 Classic EPLD |
| Number of Macrocells | 24 | — |
| Usable Gates | 450 (typical) | — |
| Propagation Delay (tPD) | 12 ns (max) | 25 ns |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Nominal Supply | 5 V | — |
| Memory Technology | UV-erasable CMOS EPROM | — |
| 封裝 | 28-PLCC (J-Lead, 11.5 x 11.5 mm) | 44-pin JLCC (windowed ceramic) |
| 安裝類型 | Surface Mount | Surface Mount |
| 工作溫度 | -40 °C to +85 °C (industrial grade, 'I' suffix) | -40C to +85C (industrial) |
| Configuration Storage | Non-volatile EPROM (instant-on) | — |
| Programming Method | Altera programming algorithm (serial/parallel master-slave) | — |
| MSL 等級 | [DATA_NEEDED: MSL level] | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | non_compliant (ceramic windowed package) |
| 腳位數 | 28 | — |
| Feedback Paths | 16 dedicated | — |
| Macrocells | — | 24 |
| User I/O Pins | — | 36 |
| Internal Frequency (fMAX) | — | [DATA_NEEDED: fMAX rating] |
| Logic Blocks | — | Sum-of-products AND/OR array |
| Technology | — | CMOS EPROM (UV-erasable) |
| Configuration Memory | — | Non-volatile EPROM (windowed ceramic) |
| 供應電壓 | — | 5 V |
| Development Tool | — | Altera MAX+PLUS II (legacy) |
| 生命週期狀態 | — | Obsolete - last time buy was late 1990s |