EP910ILC-25 vs EP910IDC-15 比較
詳細並排比較 EP910ILC-25 由 Intel 與 EP910IDC-15 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910ILC-25 | EP910IDC-15 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | EP910 Classic EPLD | Classic EPLD |
| Macrocells | 24 | 24 |
| User I/O Pins | 36 | — |
| Propagation Delay (tPD) | 25 ns | — |
| Internal Frequency (fMAX) | [DATA_NEEDED: fMAX rating] | — |
| Logic Blocks | Sum-of-products AND/OR array | — |
| Technology | CMOS EPROM (UV-erasable) | — |
| Configuration Memory | Non-volatile EPROM (windowed ceramic) | — |
| 封裝 | 44-pin JLCC (windowed ceramic) | 40-pin CDIP (Ceramic DIP, through-hole) |
| 安裝類型 | Surface Mount | — |
| 工作溫度 | -40C to +85C (industrial) | — |
| 供應電壓 | 5 V | — |
| Development Tool | Altera MAX+PLUS II (legacy) | — |
| RoHS 狀態 | non_compliant (ceramic windowed package) | non_compliant (ceramic DIP contains lead) |
| 生命週期狀態 | Obsolete - last time buy was late 1990s | — |
| Manufacturer | — | Altera (now Intel PSG) |
| Equivalent Gates | — | 450 |
| Flip-Flops | — | 48 |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Maximum Frequency (fCNT) | — | 66.6 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Terminal Count | — | 40 |
| Terminal Form | — | Through-Hole |
| Temperature Grade | — | Commercial (0C to +70C) |
| Programmable Security Bit | — | Yes |
| On-board Test Circuitry | — | Yes |
| Logic Type | — | UV Erasable EPROM-based |
| I/O Pins | — | 24 |
| Dedicated Inputs | — | 10 |
| Programming Technology | — | EPROM (UV-erasable) |