EP910ILI-25 - 24-Macrocell Classic EPLD, 28ns, PLCC-44 | Altera
MPN： EP910ILI-25 ✗ 停產EP910ILI-25 概覽
What is a Classic EPLD? A Classic EPLD is an early-generation erasable programmable logic device that combines multiple PAL-type macrocells into a single package, allowing designers to replace several discrete 24-pin PALs with one part. Within the broader programmable logic hierarchy, an EPLD sits between simple SPLDs (single PAL/GAL devices) and modern CPLDs/FPGAs. EPLDs use EPROM, EEPROM, or flash memory cells to store the fuse map, are non-volatile, and are typically programmed once via a hardware programmer such as the Altera MAX+PLUS II development system.
Key features include a 25 ns pin-to-pin propagation delay, 24 macrocells interconnected by a global bus, 12 dedicated input pins, 24 I/O pins, up to 240 product terms, an on-board JTAG-compatible logic test circuitry for AC verification during production flow, and CMOS process technology that yields low power consumption. The part uses an erasable windowed package variant, allowing the device to be erased with UV light and re-programmed.
The EP910ILI-25 architecture uses a programmable AND array feeding a fixed OR array within each macrocell, with each macrocell containing a flip-flop, output enable, and feedback path. Macrocells share a single global interconnect bus that routes any macrocell output back to any other macrocell input, providing flexible logic implementation across the 24-cell fabric. This architecture is optimized for state machines, address decoding, and glue-logic replacement in 5V systems.
Typical applications include TTL/CMOS logic integration, address decoding for microprocessor systems, state machine implementation, peripheral interface glue logic, and bus arbitration logic. The industrial temperature grade (-40C to +85C) and 5V operation make it suitable for legacy industrial control systems and 5V-only designs.
When designing with the EP910ILI-25, ensure your logic fits within 24 macrocells and 240 product terms; over-utilization forces the fitter to share product terms, which can degrade timing. Use the Altera MAX+PLUS II development environment for design entry, simulation, and programming, as this is the only officially supported toolchain for the Classic EPLD family.
This page synthesizes distributor inventory, cross-reference alternatives from the EP910 series, and practical design notes not found in the legacy datasheet, helping engineers evaluate supply options for this mature, EOL-prone part.
直接替換替代品，適用於 EP910ILI-25 — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： EP910ILI-25 （相同外形與佔位） — 差異在於 Package, Family, Operating Temperature, Mounting Type, Propagation Delay (tPD).
EP910ILC-25
✅ 直接替換聯絡詢價
查看資料表 →EP910ILC-15
✅ 直接替換聯絡詢價
查看資料表 →EP910ILC-15N
✅ 直接替換聯絡詢價
查看資料表 →EP910ILC-12
✅ 直接替換聯絡詢價
查看資料表 →EP910ILC-50
✅ 直接替換聯絡詢價
查看資料表 →EP910DC-15
✅ 直接替換聯絡詢價
查看資料表 →EP910DC-30
✅ 直接替換聯絡詢價
查看資料表 →EP910ILI-25 最大額定值與電氣特性
| Product Type | EPLD (Erasable Programmable Logic Device) |
| Series | EP910 (Classic EPLD) |
| Macrocells | 24 |
| Dedicated Inputs | 12 |
| I/O Pins | 24 |
| Product Terms | 240 (maximum) |
| Propagation Delay (tPD) | 25 ns |
| Technology | CMOS, EPROM |
| Architecture | PAL-type with global interconnect bus |
| 封裝 | PLCC-44 (windowed ceramic, J-lead) |
| Operating Voltage | 5 V (4.75 V to 5.25 V) |
| 工作溫度 | -40C to +85C (Industrial) |
| Programming Method | UV-erasable (windowed), MAX+PLUS II programmer |
| Logic Test Circuitry | On-board JTAG-compatible test |
| RoHS 狀態 | Non-compliant (windowed ceramic package) |
EP910ILI-25 腳位配置
| 腳位 1 | I/O0 — Bidirectional I/O pin 0 |
| 腳位 2 | I/O1 — Bidirectional I/O pin 1 |
| 腳位 3 | I/O2 — Bidirectional I/O pin 2 |
| 腳位 4 | I/O3 — Bidirectional I/O pin 3 |
| 腳位 5 | I/O4 — Bidirectional I/O pin 4 |
| 腳位 6 | I/O5 — Bidirectional I/O pin 5 |
| 腳位 7 | I/O6 — Bidirectional I/O pin 6 |
| 腳位 8 | I/O7 — Bidirectional I/O pin 7 |
| 腳位 9 | I/O8 — Bidirectional I/O pin 8 |
| 腳位 10 | I/O9 — Bidirectional I/O pin 9 |
| 腳位 11 | I/O10 — Bidirectional I/O pin 10 |
| 腳位 12 | I/O11 — Bidirectional I/O pin 11 |
| 腳位 13 | I/O12 — Bidirectional I/O pin 12 |
| 腳位 14 | I/O13 — Bidirectional I/O pin 13 |
| 腳位 15 | I/O14 — Bidirectional I/O pin 14 |
| 腳位 16 | I/O15 — Bidirectional I/O pin 15 |
| 腳位 17 | I/O16 — Bidirectional I/O pin 16 |
| 腳位 18 | I/O17 — Bidirectional I/O pin 17 |
| 腳位 19 | I/O18 — Bidirectional I/O pin 18 |
| 腳位 20 | I/O19 — Bidirectional I/O pin 19 |
| 腳位 21 | I/O20 — Bidirectional I/O pin 20 |
| 腳位 22 | I/O21 — Bidirectional I/O pin 21 |
| 腳位 23 | I/O22 — Bidirectional I/O pin 22 |
| 腳位 24 | I/O23 — Bidirectional I/O pin 23 |
| 腳位 25 | IN0 — Dedicated input 0 |
| 腳位 26 | IN1 — Dedicated input 1 |
| 腳位 27 | IN2 — Dedicated input 2 |
| 腳位 28 | IN3 — Dedicated input 3 |
| 腳位 29 | IN4 — Dedicated input 4 |
| 腳位 30 | IN5 — Dedicated input 5 |
| 腳位 31 | IN6 — Dedicated input 6 |
| 腳位 32 | IN7 — Dedicated input 7 |
| 腳位 33 | IN8 — Dedicated input 8 |
| 腳位 34 | IN9 — Dedicated input 9 |
| 腳位 35 | IN10 — Dedicated input 10 |
| 腳位 36 | IN11 — Dedicated input 11 |
| 腳位 37 | VCC — 5V power supply |
| 腳位 38 | GND — Ground |
| 腳位 39 | NC — Not connected (per datasheet) |
| 腳位 40 | NC — Not connected (per datasheet) |
| 腳位 41 | NC — Not connected (per datasheet) |
| 腳位 42 | NC — Not connected (per datasheet) |
| 腳位 43 | NC — Not connected (per datasheet) |
| 腳位 44 | NC — Not connected (per datasheet) |
典型應用
EP910ILI-25 適用於 7 應用s: TTL/CMOS Glue Logic Integration, Microprocessor Address Decoding, State Machine Implementation, Peripheral Interface Glue Logic, Bus Arbitration Logic, Legacy System Maintenance and Repair, Educational and Prototyping Platform.
TTL/CMOS Glue Logic Integration
The EP910ILI-25's 24-macrocell capacity and 25 ns propagation delay make it ideal for replacing multiple discrete 24-pin PAL/GAL devices in legacy 5V systems. With 12 dedicated inputs and 24 bidirectional I/O pins, the device can consolidate address decoding, bus arbitration, and peripheral control logic onto a single PLCC-44 footprint. The industrial -40C to +85C temperature grade supports factory-floor equipment where modern CPLDs are over-specified. Program the device using MAX+PLUS II to maintain design file compatibility with existing 1990s-era schematics.
推薦
Microprocessor Address Decoding
Use the EP910ILI-25 as a centralized address decoder for 8086, 68000, or Z80 microprocessor systems where multiple chip-select signals are required. The 24 macrocells can implement 8 to 12 independent address-decoded chip selects with overlapping address windows, replacing an entire board of 74LS138 decoder ICs. The 25 ns propagation delay adds minimal wait-state overhead, and the 240 product-term budget comfortably accommodates complex memory-map decoding schemes with multiple enable and qualification signals.
推薦
State Machine Implementation
The EP910ILI-25's macrocell architecture includes dedicated D flip-flops in each cell, making it well-suited for implementing multi-state control sequences in industrial controllers and test equipment. Each macrocell can be configured as registered or combinatorial output, supporting Mealy and Moore state machines with 24 states. The global interconnect bus routes any macrocell output back to any other macrocell input, simplifying state-encoding logic. Industrial temperature grade ensures reliable operation in factory automation, machine tool, and process control environments.
推薦
Peripheral Interface Glue Logic
The EP910ILI-25 bridges incompatible peripheral interfaces by implementing custom protocol converters, handshaking logic, and timing generators between ISA, VME, or proprietary buses. With 24 I/O pins and 12 dedicated inputs, the device can buffer and adapt signals between 8-bit and 16-bit peripherals, generate wait states, and arbitrate shared interrupts. The 5V CMOS I/O directly interfaces with TTL peripherals without external level shifters, simplifying legacy peripheral integration in industrial PCs and embedded controllers.
推薦
Bus Arbitration Logic
Implement multi-master bus arbitration, DMA control, and bus-request prioritization using the EP910ILI-25's macrocell fabric. The 24 macrocells easily handle 4 to 6 master arbitration trees with priority encoding, hold acknowledge timing, and bus grant logic. The 25 ns propagation delay is sufficient for standard ISA and VME bus arbitration timing budgets. Industrial temperature operation supports use in chassis with multiple competing bus masters in factory automation and telecommunications backplane applications.
推薦
Legacy System Maintenance and Repair
The EP910ILI-25's primary modern use case is maintaining and repairing legacy equipment originally built in the 1990s and early 2000s. Industrial, military, medical, and telecommunications systems with 20+ year service lives often contain Classic EPLDs that have failed or require firmware updates. Sourcing verified EP910ILI-25 stock from authorized distributors like Rochester Electronics allows field service organizations to repair systems without PCB redesign. The UV-erasable windowed package also supports re-programming after logic updates.
推薦
Educational and Prototyping Platform
The EP910ILI-25 serves as a teaching platform for digital logic and programmable logic courses, illustrating classic PAL-type architecture, macrocell design, and JTAG test circuitry before students transition to modern CPLDs and FPGAs. Universities and training centers use the device in laboratories to teach programmable logic fundamentals, including AND-OR array programming, product term allocation, and macrocell configuration. The PLCC-44 package with socket is easy to handle in educational lab environments.
推薦
推薦產品摘要
工程參考資料，適用於 EP910ILI-25 — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | EP910ILC-25 | EP910ILC-15 | EP910ILC-15N | EP910ILC-12 | EP910ILC-50 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | PLCC-44 | PLCC-44 - same | PLCC-44 - same | PLCC-44 - same | PLCC-44 - same | PLCC-44 - same |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 |
| Propagation Delay (tPD) | 25 ns | 25 ns | 15 ns | 15 ns | 12 ns | 50 ns |
| Operating Temperature | -40C to +85C (Industrial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) |
| Dedicated Inputs | 12 | 12 | 12 | 12 | 12 | 12 |
| I/O Pins | 24 | 24 | 24 | 24 | 24 | 24 |
| Product Terms | 240 | 240 | 240 | 240 | 240 | 240 |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
主要差異化特點
- Industrial temperature grade for harsh environments (對比EP910ILC-25)
- Windowed UV-erasable ceramic package (對比EP910ILC-25 (plastic))
- Logic test circuitry for production verification (對比Legacy PAL/GAL discrete logic)
設計說明
The Classic EPLD EP910ILI-25 uses Altera-proprietary macrocell architecture and is programmed only via the legacy MAX+PLUS II development system (version 9.23 or earlier). Do not attempt to use modern Intel Quartus Prime, which does not support the Classic EPLD family. Source the original MAX+PLUS II tool from Intel's legacy software archive. Without this tool, the JEDEC fuse map cannot be generated, and the device cannot be programmed even if physically intact.
Ensure your design fits within 24 macrocells and 240 product terms; over-utilization forces the fitter to share product terms between macrocells, which can degrade timing closure by 20-40%. Run the MAX+PLUS II fitter report and verify that the 'Total product terms used' is below 240 and 'Total macrocells used' is at or below 24. If either limit is exceeded, refactor the design to use fewer macrocells or migrate to a larger Classic EPLD (EP1810) or MAX 7000 series.
The PLCC-44 windowed ceramic package requires a PLCC-44 socket (e.g., 3M 8444-21B1-RK or equivalent) for programming and rework. The quartz erasure window is fragile and must be protected from mechanical damage and prolonged UV exposure during handling. Place the socket with adequate clearance above the PCB to allow UV eraser access. Add a label or mechanical cover to prevent accidental window damage in production environments where field service is required.
The EP910ILI-25 operates from a single 5V supply (4.75V to 5.25V) with CMOS-level input thresholds. Decouple VCC with a 0.1uF ceramic capacitor placed within 5mm of the VCC pin, and add a 10uF tantalum bulk capacitor on the supply rail. The device draws approximately 50-150 mA active current depending on switching activity and output loading. Use a well-regulated linear supply rather than a switching regulator to avoid injecting switching noise into the EPLD's analog sensing circuitry.
Although the EP910ILI-25 is rated for industrial -40C to +85C operation, the windowed ceramic package (J-lead PLCC-44) has limited thermal dissipation. Estimated: at maximum 150 mA active current with 5V supply, internal dissipation is approximately 0.75W. The PLCC-44 ceramic junction-to-ambient thermal resistance is approximately 35-45 C/W, so junction temperature rise above ambient is roughly 26-34C. For enclosed or high-ambient-temperature installations, verify junction temperature does not exceed 125C by adding thermal relief copper pours beneath and around the package.
合規資訊
Windowed ceramic package contains lead-based ceramic and is not RoHS compliant. REACH compliance assumed for legacy Altera parts. Not AEC-Q100 qualified. Conflict minerals compliance per Altera/Intel policy.
