EP910IPC-15 vs EP910LI-15 比較
詳細並排比較 EP910IPC-15 由 Altera 與 EP910LI-15 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910IPC-15 | EP910LI-15 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | 啟用中 |
| Device Family | Altera Classic EPLD (EP910 series) | Altera Classic EPLD |
| Product Type | Erasable Programmable Logic Device (EPLD) | Programmable Logic Device (PLD) |
| Architecture | PAL-type, CMOS | — |
| Macrocells | 24 | — |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 24 | — |
| Product Terms | 240 | — |
| External Clocks | 2 | — |
| Propagation Delay (tPD) | 15 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| 工作溫度 | 0C to +70C (commercial, IPC suffix) | — |
| 封裝 | PDIP-40 (Plastic DIP, 40-pin) | 44-terminal J-lead ceramic chip carrier (PQCC44) |
| 安裝類型 | Through-Hole | — |
| Process Technology | CMOS | — |
| Programming Method | JEDEC fuse map via Altera EPLD programmer | — |
| 腳位數 | 40 | — |
| RoHS 狀態 | [DATA_NEEDED: rohs status not confirmed in verified data] | unknown |
| Part Number | — | EP910LI-15 |
| Supply Voltage Range | — | 4.5 V to 5.5 V |
| Input/Output Lines | — | 24 |
| Total User-Signal Resources | — | 36 |
| Speed Grade | — | 15 ns |
| 工作溫度範圍 | — | -40 °C to +85 °C |
| Technology | — | CMOS |
| Package Pin Count | — | 44 terminals |
| Package Mounting | — | Surface Mount |
| Dielectric/Construction | — | Ceramic |
| REACH Status | — | unknown |
| AEC-Q100 Status | — | not_applicable |
| Lead-Free Status | — | unknown |
| Halogen-Free Status | — | unknown |
| Conflict Minerals Status | — | unknown |