EP910IPC-50 vs EP910ILC-25 比較
詳細並排比較 EP910IPC-50 由 Altera 與 EP910ILC-25 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910IPC-50 | EP910ILC-25 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Product Type | Erasable Programmable Logic Device (EPLD) | — |
| Family | Altera Classic EPLD | EP910 Classic EPLD |
| Logic Capacity | [DATA_NEEDED: macrocell count / equivalent gates] | — |
| Propagation Delay (tPD) | 50 ns | 25 ns |
| Clock-to-Output (tCO) | 35 ns | — |
| Maximum Toggle Frequency | [DATA_NEEDED: fMAX] | — |
| User I/O Pins | 24 | 36 |
| 封裝 | 40-pin Ceramic DIP (IPC, windowed) | 44-pin JLCC (windowed ceramic) |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| 工作溫度 | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Technology | CMOS EPROM cell | CMOS EPROM (UV-erasable) |
| Programming Method | Off-board EPROM programmer + UV erase | — |
| Erasure Method | UV light through ceramic window (IPC package) | — |
| 安裝類型 | Through-Hole (DIP) | Surface Mount |
| RoHS 狀態 | [DATA_NEEDED: not stated in verified data] | non_compliant (ceramic windowed package) |
| Macrocells | — | 24 |
| Internal Frequency (fMAX) | — | [DATA_NEEDED: fMAX rating] |
| Logic Blocks | — | Sum-of-products AND/OR array |
| Configuration Memory | — | Non-volatile EPROM (windowed ceramic) |
| 供應電壓 | — | 5 V |
| Development Tool | — | Altera MAX+PLUS II (legacy) |
| 生命週期狀態 | — | Obsolete - last time buy was late 1990s |