EP910LC-30Y vs EP910LC-32 比較
詳細並排比較 EP910LC-30Y 由 Altera 與 EP910LC-32 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910LC-30Y | EP910LC-32 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | Altera Classic EPLD | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 24 | — |
| Usable Gates | 450 | — |
| Pin-to-Pin Delay (tPD) | 30 ns | — |
| Counter Frequency (fMAX) | 100 MHz (family maximum) | — |
| 供應電壓 | 5 V (TTL-compatible) | — |
| Process Technology | CMOS, UV-erasable / OTP | — |
| 封裝 | PLCC-44 | PLCC-32 |
| 工作溫度 | Commercial 0C to +70C | — |
| Speed/Power Grade | LC (low-power, 30ns) | — |
| Processing Flow | Y (extended reliability) | — |
| Logic Compatibility | 100% TTL emulation | — |
| 安裝類型 | Surface Mount (PLCC socket) | Surface Mount (PLCC socket or direct solder) |
| RoHS 狀態 | [DATA_NEEDED: RoHS status not specified in retrieved data] | unknown |
| Device Family | — | Altera Classic EPLD |
| Number of Macrocells | — | 24 |
| Number of Usable Gates | — | 900 gates (typical) |
| Number of Dedicated Inputs | — | 10 |
| Number of I/O Pins | — | 20 |
| Speed Grade | — | -32 |
| Maximum Toggle Frequency (fMAX) | — | [DATA_NEEDED: fMAX value in MHz for -32 grade] |
| Pin-to-Pin Propagation Delay (tPD) | — | [DATA_NEEDED: tPD in ns for -32 grade] |
| Supply Voltage (VCC) | — | 5 V |
| Logic Family | — | Low-power CMOS (LC suffix) |
| Programming Method | — | UV-erasable or one-time programmable (OTP for LC windowless variant) |
| 工作溫度範圍 | — | [DATA_NEEDED: commercial or industrial grade] |
| I/O Standard | — | TTL-compatible |
| MSL 等級 | — | unknown |