EP910LC-35T vs EP910LC44-35 比較
詳細並排比較 EP910LC-35T 由 Altera 與 EP910LC44-35 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910LC-35T | EP910LC44-35 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | NRND |
| Family | Classic EPLD (EP910) | Classic EPLD (OT sub-family) |
| Logic Capacity | 450 usable gates | — |
| Macrocells | 24 | 24 |
| Propagation Delay (tPD) | 35 ns | 35 ns (max) |
| Maximum Operating Frequency | 28.6 MHz | — |
| Supply Voltage (VCC) | 5 V | 5 V (single supply) |
| User I/O Pins | 36 | — |
| 封裝 | PLCC-44 (J-lead) | 44-pin PLCC (J-leaded) |
| Process Technology | CMOS (EPROM-based) | CMOS |
| 工作溫度 | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Erasure Method | UV-erasable window (ceramic package) / OTP (plastic) | — |
| Programming | Altera programming hardware + MAX+PLUS II | — |
| 安裝類型 | Surface Mount (PLCC socket or solder) | Surface Mount |
| MSL 等級 | MSL 3 (168 hours) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status not in verified data] | — |
| Architecture | — | PAL-type AND/OR array |
| Usable Gates | — | 450 |
| Maximum Frequency (fMAX) | — | 28.6 MHz |
| Total Inputs | — | 36 |
| I/O Pins | — | 24 |
| Global Clocks | — | 2 |
| Programmability | — | UV-erasable (windowed ceramic) |