EP910LC-40H vs EP910LC-35 比較
詳細並排比較 EP910LC-40H 由 Altera 與 EP910LC-35 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910LC-40H | EP910LC-35 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Classic EPLD (EP910) | Classic (EP910) |
| Macro Cells | 24 | — |
| Usable Gates | 450 | 450 |
| Logic Elements | 24 macro cells / expandable to 48 via expander terms | — |
| Propagation Delay (tPD) | 40 ns max | 35 ns |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V |
| Supply Current (ICC) | Low-power CMOS, typical ICC < 100 mA | — |
| Technology | CMOS, UV-erasable EPROM | CMOS EPROM |
| 封裝 | 40-pin Ceramic DIP (CDIP-40), JEDEC standard | PLCC-44 (J-lead, LC suffix) |
| 安裝類型 | Through-Hole (THT) | — |
| 工作溫度 | -40C to +85C (industrial) [DATA_NEEDED: confirm exact temp grade] | 0C to +70C (commercial) |
| Speed Grade | -40 (40 ns tPD) | — |
| Programming Method | UV-erase + EPROM program, ~100 erase cycles | — |
| I/O Pins | [DATA_NEEDED: I/O count - datasheet indicates 36 user I/O typical] | — |
| RoHS 狀態 | [DATA_NEEDED: not confirmed from datasheet - non-RoHS likely given vintage ceramic DIP] | Not applicable (legacy product) |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Macrocells | — | 24 |
| Maximum Toggle Frequency | — | 28.6 MHz |
| 腳位數 | — | 44 |
| Programmable Flip-Flops | — | Yes (per macrocell) |
| Output Enable Control | — | Per macrocell |
| Erasure Method | — | UV (windowed) or OTP (plastic) |