EP910LC-40H vs EP910LC-40 比較
詳細並排比較 EP910LC-40H 由 Altera 與 EP910LC-40 由 Rochester Electronics. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Rochester Electronics
EP910LC-40 - 450-Gate CMOS EPLD, 40ns, PQCC-44 | Rochester / Altera
EP910LC-40 Obsolete規格比較
| 參數 | EP910LC-40H | EP910LC-40 |
|---|---|---|
| 品牌 | Altera | Rochester Electronics |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Classic EPLD (EP910) | — |
| Macro Cells | 24 | — |
| Usable Gates | 450 | 450 |
| Logic Elements | 24 macro cells / expandable to 48 via expander terms | — |
| Propagation Delay (tPD) | 40 ns max | 40 ns |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V (single supply) |
| Supply Current (ICC) | Low-power CMOS, typical ICC < 100 mA | — |
| Technology | CMOS, UV-erasable EPROM | CMOS EPROM |
| 封裝 | 40-pin Ceramic DIP (CDIP-40), JEDEC standard | PQCC-44 (Plastic Leaded Chip Carrier, J-lead) |
| 安裝類型 | Through-Hole (THT) | — |
| 工作溫度 | -40C to +85C (industrial) [DATA_NEEDED: confirm exact temp grade] | — |
| Speed Grade | -40 (40 ns tPD) | — |
| Programming Method | UV-erase + EPROM program, ~100 erase cycles | Altera Logic Programmer (PLAD-J), 4-wire serial |
| I/O Pins | [DATA_NEEDED: I/O count - datasheet indicates 36 user I/O typical] | — |
| RoHS 狀態 | [DATA_NEEDED: not confirmed from datasheet - non-RoHS likely given vintage ceramic DIP] | Not applicable (legacy) |
| Manufacturer | — | Rochester Electronics (Altera original) |
| Device Family | — | Altera Classic EPLD - EP910 |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Macrocells | — | 24 |
| Logic Array Blocks | — | 2 (12 macrocells each) |
| Maximum Toggle Frequency (fMAX) | — | 25 MHz |
| User I/O Pins | — | 36 |
| Dedicated Inputs | — | 4 |
| Operating Temperature (Commercial) | — | 0 C to +70 C |
| Lead-Free Status | — | Not applicable |