EP910LI-40 vs EP910LI-40T 比較
詳細並排比較 EP910LI-40 由 Altera 與 EP910LI-40T 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910LI-40 | EP910LI-40T |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Manufacturer | Altera (now Intel PSG) | — |
| Product Family | Classic EPLD - EP910 series | — |
| Device Type | Erasable Programmable Logic Device (EPLD) | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 24 bidirectional | 24 |
| Maximum Logic Inputs | 36 | — |
| Product Terms | 240 | 240 |
| Propagation Delay (tPD) | 40 ns | 40 ns |
| Technology | Low-power CMOS (L-suffix) | CMOS, UV-erasable EPROM |
| 工作溫度 | -40C to +85C (industrial, I-suffix) | -40C to +85C (Industrial) |
| 封裝 | PLCC-44 (J-lead, windowed ceramic) | Tape and Reel (suffix T); 40-pin DIP / 44-pin PLCC |
| 安裝類型 | Surface Mount (socket-compatible) | — |
| Programmability | UV-erasable, JEDEC-standard algorithm | — |
| RoHS 狀態 | Non-compliant (windowed ceramic PLCC, legacy) | [DATA_NEEDED: rohs status] |
| Lifecycle | Obsolete - replaced by MAX 7000 / MAX II CPLD family | — |
| Family | — | Classic EPLD |
| Maximum Inputs | — | 36 |
| Maximum Outputs | — | 24 |
| 供應電壓 | — | 5 V (typical) |
| Architecture | — | PAL-type with global bus |
| Programming Method | — | Altera Master Programming Unit (MPU), no JTAG |