EP910PC-15 vs EP910PC-35 比較
詳細並排比較 EP910PC-15 由 Altera 與 EP910PC-35 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910PC-15 | EP910PC-35 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Altera Classic EPLD | Classic EPLD |
| Usable Gates | 900 | — |
| Macrocells | 24 | 24 |
| Maximum Pin-to-Pin Delay (tpd) | 15 ns | — |
| Counter Frequency (fCNT) | 100 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| Supply Current (Icc) | 80 mA typical | — |
| Dedicated Inputs | 10 | 12 |
| Dedicated I/O Pins | 12 | — |
| 工作溫度 | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| 封裝 | 24-pin PDIP (PDIP-24, 0.300 inch) | 40-pin PDIP (Plastic DIP) |
| 安裝類型 | Through-Hole | Through-Hole |
| Process Technology | CMOS, UV-erasable | — |
| Programming Method | Altera Logic Programmer card | UV-erase (ceramic) / OTP (plastic), A+PLUS / MAX+PLUS tools |
| RoHS 狀態 | [DATA_NEEDED: RoHS status - EP910 is a legacy through-hole part, likely non-RoHS] | — |
| MSL 等級 | Not applicable (through-hole) | — |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| I/O Pins | — | 24 |
| Total Inputs | — | 36 |
| Product Terms | — | 240 |
| Propagation Delay (tPD) | — | 35 ns |
| Maximum Counter Frequency | — | 37 MHz |
| Internal Performance Frequency | — | 100 MHz |
| Technology | — | CMOS, UV-erasable/OTP |
| 供應電壓 | — | 5 V |
| Architecture | — | PAL-type sum-of-products, AND/OR array |
| Compliance / RoHS | — | [DATA_NEEDED: RoHS status - legacy part] |