EP910PC-20 vs EP910PC30T 比較
詳細並排比較 EP910PC-20 由 Altera 與 EP910PC30T 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910PC-20 | EP910PC30T |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Device | EP910 | — |
| Usable Gates | 900 | — |
| Macrocell Count | [DATA_NEEDED: macrocell count] | — |
| Pin-to-Pin Delay (tPD) | 20 ns | — |
| 封裝 | PDIP-24 (PC suffix) | 24-pin PDIP (PC) |
| 腳位數 | 24 | 24 |
| Supply Voltage (VCC) | 5 V | 5 V (4.75 V to 5.25 V) |
| Technology | CMOS EPROM (UV-erasable) | — |
| I/O Compatibility | 100% TTL | — |
| 工作溫度 | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| Programming Method | EPROM programmer, JEDEC fuse map | — |
| 安裝類型 | Through-Hole (DIP) | Through-Hole (THT) |
| MSL 等級 | [DATA_NEEDED: MSL level] | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Device Series | — | EP910 |
| Number of Macrocells | — | 24 |
| Number of I/O Pins | — | 24 |
| Number of Dedicated Inputs | — | 12 |
| Maximum Product Terms | — | 240 |
| Propagation Delay (tPD) | — | 30 ns |
| Maximum Clock Frequency (fMAX) | — | 33.3 MHz |
| Process Technology | — | CMOS |
| Programmable Logic Architecture | — | PAL-type sum-of-products, EPLD |
| Speed Grade | — | -30 (30 ns tPD) |
| Programming Technology | — | EPROM (OTP in plastic package, UV-erasable in windowed package) |