EP910PI-30T vs EP910PI-12T 比較
詳細並排比較 EP910PI-30T 由 Altera 與 EP910PI-12T 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910PI-30T | EP910PI-12T |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | 24 |
| Usable Gates | 480 | — |
| Dedicated Inputs | 10 | 12 |
| Propagation Delay (tPD) | 30 ns | 12 ns |
| Register (Clock-to-Output) Delay | 20 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V (4.75 V min, 5.25 V max) |
| Technology | CMOS, UV-erasable (windowed ceramic) | — |
| Package Type | 40-pin PDIP (ceramic windowed) | — |
| 安裝類型 | Through-Hole | — |
| 工作溫度 | -40 C to +85 C (industrial) | 0C to +70C (commercial) |
| Programming | Altera Classic device programmer / MAX+PLUS II flow | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | Non-compliant (legacy PDIP package, contains lead) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Maximum Operating Frequency | — | 76.9 MHz |
| Logic Gates | — | [DATA_NEEDED: logic gate count] |
| I/O Pins | — | 24 |
| External Clock Inputs | — | 2 |
| Outputs | — | 24 |
| Terminals / Pin Count | — | 44 (PDIP-40 package pinout with NC pins) |
| 封裝 | — | 40-pin PDIP (Plastic DIP) |
| Process Technology | — | CMOS |
| Programmable Technology | — | UV-erasable EPROM |
| Programming Interface | — | JEDEC-standard |
| 生命週期狀態 | — | NRND / EOL (mature legacy product) |