EPC1213LC20 vs EPC1LC20C 比較
詳細並排比較 EPC1213LC20 由 Intel 與 EPC1LC20C 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPC1213LC20 | EPC1LC20C |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | EEPROM | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| 記憶體類型 | OTP Configuration PROM (Flash-based) | Serial Configuration Flash |
| 記憶體容量 | 212 Kbit | 1 Mbit (1,048,576 bits) |
| 介面 | Serial (Altera FPGA configuration protocol) | Serial (DATA/DCLK) + JTAG (IEEE 1149.1) |
| Maximum Configuration Clock | 6 MHz | — |
| Supply Voltage (Core) | 5.0 V | — |
| I/O Voltage Tolerance | 3.3 V / 5.0 V | — |
| Programmability | One-Time Programmable (OTP) via IEEE 1149.1 JTAG | In-system via JTAG |
| In-System Programmability | Yes (5.0 V and 3.3 V ISP) | — |
| Supported FPGA Families | ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX | — |
| Compression Support | Yes (FPGA decompresses bitstream during load) | — |
| 工作溫度 | 0C to +70C (Commercial) | -40C to +85C (industrial) |
| 封裝 | 20-PLCC (J-lead, 9x9 mm) | 20-pin LCC (Leadless Chip Carrier) |
| Package Code | QCCJ | — |
| 安裝類型 | Surface Mount | Surface Mount (ceramic) |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance status] |
| Configuration Clock (DCLK) | — | 8 MHz maximum |
| 供應電壓 | — | 3.3 V or 5.0 V |
| Cascading Support | — | Yes (nCS, CS pins) |
| Compatible FPGA Families | — | FLEX 10K, ACEX 1K, APEX 20K |
| JTAG Pins | — | TCK, TMS, TDI, TDO |
| Configuration Mode | — | Slave-serial (FPGA-master) |
| MSL 等級 | — | MSL3 (ceramic, floor life 168 hours) |