EPC16QC100II vs EPC16QC100DM 比較

詳細並排比較 EPC16QC100II 由 Altera 與 EPC16QC100DM 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC16QC100II EPC16QC100DM
品牌 Altera Intel
類別 Memory ICs Memory ICs
生命週期狀態 NRND NRND
記憶體類型 FPGA Configuration PROM (Flash-based) Non-volatile Configuration PROM (NOR flash)
Memory Density 16 Mbit 16 Mbit (2 Mbyte)
Supported FPGA Families APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, FLEX 8000, Cyclone —
Configuration Mode FPP / PSA (Fast Passive Parallel / Passive Serial Asynchronous) —
Programmability In-System Programmable via IEEE 1149.1 (JTAG) —
Cascade Support Yes (multi-PROM cascading supported) —
Core Supply Voltage 3.3 V —
I/O Tolerance 5 V tolerant configuration pins —
封裝 100-pin PQFP (Plastic Quad Flat Pack) 100-pin PQFP (QFPA)
Package Dimensions 20 mm x 14 mm, 0.5 mm pitch —
Lead Finish Matte Tin (lead-free) —
工作溫度 -40C to +85C (Industrial) —
MSL 等級 3 (per JEDEC J-STD-020) [DATA_NEEDED: MSL rating]
RoHS 狀態 Compliant —
Configuration Pins DCLK, DATA[0..n], nCONFIG, nSTATUS, CONF_DONE, OE —
Compression Support Yes (reduces on-PROM footprint vs uncompressed bitstream) —
Configuration Interface — Serial (SPI-compatible, Altera FPP mode)
Core Supply Voltage (VCC) — 3.0 V to 3.6 V
I/O Voltage (VIO) — 2.5 V / 3.3 V selectable
Output Voltage (VPP) — 1.8 V / 2.5 V / 3.3 V selectable
Maximum DCLK Frequency — 40 MHz
Cascadable — Yes (multi-device daisy chain via nCASC)
In-System Programming — Yes (IEEE 1532 / JTAG)
Program/Erase Cycles — [DATA_NEEDED: program/erase cycle endurance]
Data Retention — [DATA_NEEDED: data retention years]
工作溫度範圍 — -40 C to +85 C (industrial)
Package Code — Q100 + DM suffix
Lead-Free / RoHS — [DATA_NEEDED: lead-free status]
Compatible FPGA Families — Stratix, Cyclone, APEX, ACEX

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