EPC16QC100N vs EPC16QC100II 比較

詳細並排比較 EPC16QC100N 由 Altera 與 EPC16QC100II 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC16QC100N EPC16QC100II
品牌 Altera Altera
類別 Memory ICs Memory ICs
生命週期狀態 Obsolete NRND
記憶體容量 16 Mbit (16,777,216 bits) —
Programmable Type In System Programmable —
Configuration Clock Frequency 33 MHz max —
On-Chip Decompression Yes (supports compressed bitstreams) —
Supply Voltage (VCC) 3.0 V to 3.6 V —
Access Time 90 ns typical —
Flash Read Bandwidth 160 Mbps (16-bit DQ at 10 MHz) —
Configuration Interface FPP / PS / AS via dedicated FPGA pins —
JTAG (IEEE 1149.1) ISP Supported —
工作溫度 0 C to 70 C -40C to +85C (Industrial)
封裝 100-pin PQFP (20 x 14 mm) 100-pin PQFP (Plastic Quad Flat Pack)
安裝類型 Surface Mount —
Lead Free Yes (per datasheet) —
Packaging Tray —
Supported FPGA Families ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, FLEX 8000, Cyclone
記憶體類型 — FPGA Configuration PROM (Flash-based)
Memory Density — 16 Mbit
Configuration Mode — FPP / PSA (Fast Passive Parallel / Passive Serial Asynchronous)
Programmability — In-System Programmable via IEEE 1149.1 (JTAG)
Cascade Support — Yes (multi-PROM cascading supported)
Core Supply Voltage — 3.3 V
I/O Tolerance — 5 V tolerant configuration pins
Package Dimensions — 20 mm x 14 mm, 0.5 mm pitch
Lead Finish — Matte Tin (lead-free)
MSL 等級 — 3 (per JEDEC J-STD-020)
RoHS 狀態 — Compliant
Configuration Pins — DCLK, DATA[0..n], nCONFIG, nSTATUS, CONF_DONE, OE
Compression Support — Yes (reduces on-PROM footprint vs uncompressed bitstream)

資料表與資源

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