EPC1LC120 vs EPC1L120 比較
詳細並排比較 EPC1LC120 由 Altera 與 EPC1L120 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPC1LC120 | EPC1L120 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | Memory ICs | Memory ICs |
| 生命週期狀態 | 啟用中 | 最後購買 |
| 記憶體類型 | Serial Configuration Memory (Flash-based, non-volatile) | Configuration EEPROM |
| Memory Density | 1 Mbit | — |
| Serial Clock Frequency (DCLK) | 8 MHz | — |
| Supported FPGA Families | APEX 20K, ACEX 1K, Cyclone, MAX, Mercury, Stratix-class | — |
| 介面 | Altera / Intel proprietary FPGA-configuration serial bus (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) | — |
| 封裝 | LQFP-120 (Low-profile Quad Flat Pack) | PLCC-20 |
| 安裝類型 | Surface Mount | Surface Mount / Through-Hole (socket) |
| 工作溫度範圍 | [DATA_NEEDED: operating temperature range] | — |
| 供應電壓 | [DATA_NEEDED: VCC range] | — |
| Programming | Factory / JTAG via Altera programming tools | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| MSL 等級 | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: MSL level] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Configuration Mode | Serial configuration of SRAM-based FPGAs | — |
| Compatible Bitstream Width | Serial | — |
| Memory Capacity | — | 120 kbit |
| 介面類型 | — | Serial (Altera configuration protocol) |
| 工作電源電壓 | — | 3.3 V / 5 V |
| Output Compatibility | — | MultiVolt: 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V |
| Programmability | — | In-System via JTAG (IEEE 1149.1) |
| JTAG Support | — | Yes (dedicated JTAG port) |
| Reprogram Cycles | — | 100 cycles typical |
| 工作溫度 | — | -40C to +85C (industrial) |
| Compatible Altera FPGAs | — | FLEX 6000, FLEX 8000, MAX 7000, MAX 9000 families |
| Cascade Support | — | Yes (multi-FPGA configuration chains) |