EPC2C20 vs EPC2CC20N 比較

詳細並排比較 EPC2C20 由 Altera 與 EPC2CC20N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Altera
EPC2C20 EPC2C20 - Altera FPGA Configuration Device

EPC2C20 - Altera FPGA Configuration Device

EPC2C20 ✓ 啟用中

規格比較

參數 EPC2C20 EPC2CC20N
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 啟用中 NRND
Manufacturer Altera —
MPN EPC2C20 —
Device Type Configuration device integrated circuit —
Primary Function Configuration of SRAM-based lookup-table devices —
Configuration Architecture Single-device configuration solution —
Architecture Block 1 Configuration controller —
Architecture Block 2 Flash memory —
Memory Technology Flash memory —
Supported Device Class SRAM-based LUT devices —
Configuration Mode [DATA_NEEDED: configuration mode] —
Memory Density [DATA_NEEDED: memory density] —
Configuration Data Interface [DATA_NEEDED: configuration data interface] —
Operating Voltage [DATA_NEEDED: operating voltage] —
Configuration Clock Frequency [DATA_NEEDED: configuration clock frequency] —
封裝 [DATA_NEEDED: package] PLCC-20
腳位數 [DATA_NEEDED: pin count] —
工作溫度範圍 [DATA_NEEDED: operating temperature range] —
RoHS 狀態 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance status]
REACH Status [DATA_NEEDED: REACH status] —
AEC-Q100 Qualification [DATA_NEEDED: AEC-Q100 qualification] —
功能 — Configuration device for SRAM-based LUT FPGAs
Density — [DATA_NEEDED: bitstream density in bits]
Configuration Interface — 16-bit parallel (FPP) / Passive Serial (PS)
Supply Voltage (VCC) — 3.3 V
Programming Interface — JTAG (IEEE 1149.1) via ByteBlasterMV / USB-Blaster
In-System Programmable — Yes
Error Detection — 16-bit CRC on configuration frames
Configuration Modes Supported — FPP and PS (depends on host FPGA)
Cascadable — Yes (multiple EPC2 devices for larger bitstreams)
Open-Drain Status Pin — Yes (CONF_DONE / nSTATUS compatible)
工作溫度 — [DATA_NEEDED: industrial/commercial temp range]
安裝類型 — Surface Mount (PLCC-20 socket compatible)
MSL 等級 — [DATA_NEEDED: MSL rating]

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