EPC2LC20-V vs EPC2LI20 比較
詳細並排比較 EPC2LC20-V 由 Altera 與 EPC2LI20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPC2LC20-V | EPC2LI20 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | Memory ICs | Memory ICs |
| 生命週期狀態 | Obsolete | NRND |
| 記憶體類型 | Configuration PROM (Flash-based, in-system programmable) | Flash (in-system programmable) |
| Memory Density | 1.6 Mbit | — |
| Configuration Interface | Serial (Altera FPP/PS modes via DCLK/nSTATUS/CONF_DONE) | Serial or Byte-wide (parallel) |
| Maximum Configuration Clock | 10 MHz | — |
| Supply Voltage VCC | 3.3 V | — |
| I/O Tolerance | 5 V tolerant on configuration pins | — |
| In-System Programming | Yes, via IEEE 1149.1 JTAG (TMS/TCK/TDI/TDO) | — |
| Cascade Support | Yes, daisy-chainable for >1.6 Mbit designs | — |
| Operating Temperature Range (V suffix) | 0 °C to +70 °C (commercial) | — |
| Package Type | 20-pin PLCC (JEDEC MS-018) | — |
| Package Dimensions | 9 x 9 mm body, 1.27 mm pitch | — |
| 安裝類型 | Surface Mount (PLCC socket compatible) | Surface Mount (PLCC socket-compatible) |
| Supported FPGA Families | APEX 20K, ACEX 1K, FLEX 10K, FLEX 6000, MAX 9000 | — |
| RoHS 狀態 | Compliant (per distributor listings) | [DATA_NEEDED: RoHS status] |
| Lead-Free | Yes | — |
| 記憶體容量 | — | 1.6 Mb (1,572,864 bits) |
| Programmable Type | — | In System Programmable (ISP) |
| 功能 | — | Configuration PROM for SRAM-based FPGAs |
| Supply Voltage - Operating | — | 3.0 V to 3.6 V and 4.5 V to 5.5 V (auto-sensing) |
| 工作溫度 | — | -40 C to +85 C (Industrial) |
| 封裝 / 外殼 | — | 20-PLCC (J-lead, 9x9 mm) |
| Decompression | — | On-chip (supports compressed bitstreams) |
| JTAG / ISP Interface | — | IEEE 1532 (TCK, TMS, TDI, TDO) |
| Multi-Device Support | — | Yes (daisy-chain configuration) |
| User-Accessible Memory | — | Yes (unused flash available to user logic) |
| MSL 等級 | — | [DATA_NEEDED: MSL level] |