EPC4QC100 vs EPC16QC-100T 比較

詳細並排比較 EPC4QC100 由 Altera 與 EPC16QC-100T 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC4QC100 EPC16QC-100T
品牌 Altera Altera
類別 Memory ICs Memory ICs
生命週期狀態 Obsolete Obsolete
功能 In-System Programmable Configuration PROM for FPGAs —
記憶體類型 Flash Flash Configuration PROM (in-system programmable)
記憶體容量 4 Mb —
Supply Voltage (Core and I/O) 3.3 V —
Maximum Configuration Clock 66 MHz —
介面 Serial / Fast Passive (Altera FPGAs) —
In-System Programmability IEEE Std. 1532 compliant —
JTAG Support Yes (boundary scan + ISP via Jam STAPL) —
nINIT_CONF Pin Yes (triggers FPGA configuration via private JTAG instruction) —
封裝 100-pin PQFP (20x14 mm) 100-pin PQFP (20 x 14 mm), 0.65 mm pitch
工作溫度 0C to +70C (commercial) [DATA_NEEDED: Operating temperature range]
安裝類型 Surface Mount Surface Mount
RoHS 狀態 unknown unknown
Lead-Free unknown unknown
Compatible FPGA Families Stratix, Cyclone, APEX, Mercury, ACEX —
Memory Density — 16 Mbit (2 Mbyte)
Supported FPGA Families — Stratix, APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K
Configuration Data Width — 8-bit or 16-bit (cascaded dual-device mode)
Configuration Modes — Serial (single device), Parallel (two cascaded devices)
Data Compression Support — Yes (35% to 55% bitstream reduction typical)
JTAG / Boundary Scan — IEEE 1149.1 compliant, in-system programmable
供應電壓 — 3.3 V
Cascade Interface — nCE / nOE handshake for multi-device chains
Programming Interface — JTAG (IEEE 1149.1) and serial
Endurance — [DATA_NEEDED: Program/erase cycle rating]
Data Retention — [DATA_NEEDED: Data retention specification]
MSL 等級 — [DATA_NEEDED: Moisture sensitivity level]

資料表與資源

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