EPC8QI100N vs EPC8QI100 比較

詳細並排比較 EPC8QI100N 由 Altera 與 EPC8QI100 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC8QI100N EPC8QI100
品牌 Altera Intel
類別 EEPROM Memory ICs
生命週期狀態 NRND Obsolete
Manufacturer Altera (Intel) —
Part Family EPC8 (Enhanced Configuration) —
Device Type Configuration PROM for SRAM-based FPGAs —
記憶體容量 8 Mbit (8,388,608 bits) 8 Mbit
Programmable Type In System Programmable (Flash) —
Configuration Interface Altera serial (4-wire: DATA, DCLK, nCS, nINIT_CONF) —
Maximum Configuration Clock 50 MHz —
On-Chip Decompression Yes (Altera compression algorithm) —
Supply Voltage (VCC) 3.0 V to 3.6 V —
工作溫度 -40 °C to +85 °C (Industrial) -40C to +85C (industrial)
封裝 100-PQFP / 100-BQFP (20 x 14 mm) 100-PQFP (20 x 14 mm)
腳位數 100 —
安裝類型 Surface Mount Surface Mount
Lead-Free / RoHS Yes (per distributor listings) —
JTAG (IEEE 1149.1) ISP Supported —
Multi-Device Daisy-Chain Supported —
Target FPGA Families ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX —
Packaging Tray —
記憶體類型 — Flash (NOR, Enhanced Configuration PROM)
Supply Voltage (Core) — 3.3 V
Supply Voltage (I/O) — 3.3 V
介面 — Altera FPGA configuration serial/parallel (FPP) + JTAG (IEEE 1149.1)
In-System Programmability — IEEE Std. 1532 compliant
Programming Language — Jam STAPL
Boundary Scan — JTAG boundary-scan test supported
Data Compression — Yes (increases effective capacity)
Configuration Controller — On-chip, dedicated to Altera FPGAs
Initiate-Configuration Pin — nINIT_CONF (private JTAG instruction)
Compatible FPGAs — Stratix, Stratix II, APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, Cyclone, Cyclone II, Arria GX, Stratix GX, Stratix II GX
RoHS 狀態 — Non-compliant (legacy PQFP, lead-bearing)

資料表與資源

瀏覽所有產品 建立 BOM 索取報價