EPF10K200SFC672-1 vs EPF10K200SFC672-2 比較

詳細並排比較 EPF10K200SFC672-1 由 Altera 與 EPF10K200SFC672-2 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPF10K200SFC672-1 EPF10K200SFC672-2
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete NRND
Series FLEX 10KE FLEX 10KE
Family FLEX 10KE (FLEX-10KS) —
Logic Elements / Cells 9984 —
Total RAM Bits 98304 —
Number of LABs/CLBs 1248 —
Number of User I/Os 470 —
Number of Gates 200K system gates —
Core Voltage (VCCINT) 2.5 V —
I/O Voltage (VCCIO) 2.5 V / 3.3 V / 5.0 V (multi-volt) —
Maximum Operating Frequency 250 MHz 200 MHz
Propagation Delay 0.4 ns —
Process Technology 0.22 µm CMOS, SRAM-based 0.22 µm CMOS
Package Type 672-ball FBGA (FineLine BGA), 45 x 45 mm, 1.27 mm pitch —
工作溫度 0 °C to +70 °C (Commercial) 0 °C to +70 °C (Commercial)
Programming Interface JTAG (IEEE 1149.1) + serial/parallel passive configuration —
Embedded Array Blocks (EABs) 12 —
Speed Grade -1 -2
安裝類型 Surface Mount —
MSL 等級 [DATA_NEEDED: MSL level] —
RoHS 狀態 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance status]
Logic Elements — 9,984
System Gates — 200,000
Logic Array Blocks (LABs) — 1,248
User I/O Pins — 470
Embedded Memory (bits) — 98,304
Core Supply Voltage — 2.5 V (2.375 V to 2.625 V)
I/O Supply Voltage — MultiVolt 2.5 V / 3.3 V / 5.0 V
Internal Propagation Delay — 0.4 ns
封裝 — 672-pin FineLine BGA (FBGA), 45 × 45 mm, 1.27 mm pitch
Configuration Method — SRAM-based, passive parallel asynchronous
Boundary Scan — IEEE 1149.1 (JTAG)
On-chip PLL — Yes

資料表與資源

瀏覽所有產品 建立 BOM 索取報價