EPM1270F256I5 vs EPM1270F256C5 比較
詳細並排比較 EPM1270F256I5 由 Altera 與 EPM1270F256C5 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM1270F256I5 | EPM1270F256C5 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Device Family | MAX II | — |
| Series | EPM1270 | MAX II |
| Macrocell Count | 980 | — |
| Logic Elements | 1270 | — |
| User I/O Pins | 212 (max) | — |
| User Flash Memory | 8 Kbits | 8 Kbits |
| 封裝 | 256-ball FBGA (FineLine BGA) | 256-ball FineLine BGA (FBGA-256) |
| Pin/Package Count | 256 | — |
| Process Technology | 0.18 µm | 0.18 µm |
| Supply Voltage (VCCINT) | 1.8 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V | — |
| Maximum Internal Frequency | 201.1 MHz | — |
| Pin-to-Pin Delay (tPD) | 6.2 ns | — |
| 工作溫度 | -40 °C to +100 °C (industrial, "I") | 0 °C to +85 °C (commercial, 'C' grade) |
| Speed Grade | 5 | — |
| 安裝類型 | Surface Mount | — |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | JTAG (IEEE 1149.1) / ISP via ByteBlaster / USB-Blaster |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | Compliant |
| Family | — | EPM1270 |
| Macro Cells | — | 980 |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/O Pins | — | 212 |
| Pin-to-Pin Logic Delay (tPD) | — | 6.2 ns (C5 speed grade) |
| Internal Operating Frequency | — | 201.1 MHz |
| Core Supply Voltage | — | 2.5 V / 3.3 V |
| I/O Standards Supported | — | LVCMOS/LVTTL 1.8 V, 2.5 V, 3.3 V, 5.0 V (MultiVolt) |
| Configuration Memory | — | On-chip flash (non-volatile, instant-on) |