EPM3064ATC100-10 vs EPM3064ATC100-4 比較
詳細並排比較 EPM3064ATC100-10 由 Altera 與 EPM3064ATC100-4 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM3064ATC100-10 - 64-Macrocell MAX 3000A CPLD, 100MHz, TQFP-100 | Altera
EPM3064ATC100-10 Nrnd規格比較
| 參數 | EPM3064ATC100-10 | EPM3064ATC100-4 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | NRND |
| Family | MAX 3000A | MAX 3000A |
| Logic Gates | 1250 gates | — |
| Macrocells | 64 | — |
| Logic Array Blocks | 2 | — |
| User I/O Pins | 34 | — |
| 封裝 | TQFP-100 (100-pin Thin Quad Flat Pack) | 100-pin TQFP |
| Propagation Delay (tPD) | 10 ns | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| Process Technology | CMOS EEPROM | CMOS EEPROM |
| In-System Programmability | IEEE Std. 1149.1 (JTAG) and IEEE Std. 1532 compliant | — |
| Global Clock Signals | 2 (with optional inversion) | — |
| Output Enable Signals | 6 or 10 pin- or logic-driven | — |
| Output Slew-Rate Control | Programmable | — |
| Operating Temperature Grade | Commercial | — |
| MultiVolt I/O Support | 1.5V / 1.8V / 2.5V / 3.3V interfaces | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance] | unknown |
| Device Type | — | CPLD (EEPROM-based) |
| Macro Cells | — | 64 |
| Logic Array Blocks (LABs) | — | 2 |
| Usable Gates | — | 1,250 (range 600 to 10,000 across family) |
| Maximum User I/O Pins | — | 34 |
| Pin-to-Pin Delay (tPD) | — | 4.5 ns |
| Counter Frequency (fCNT) | — | 227.3 MHz |
| Internal Performance | — | 222.2 MHz |
| Supply Voltage VCCINT | — | 3.3 V |
| I/O Voltage (MultiVolt) | — | 2.5 V / 3.3 V / 5.0 V |
| In-System Programming | — | Yes (IEEE 1149.1 JTAG) |
| 安裝類型 | — | Surface Mount |
| 工作溫度 | — | 0C to +70C (commercial) [DATA_NEEDED: industrial temp grade option] |
| Architecture | — | 5-level Altera MAX |