EPM3064ATC100-10N vs EPM3064ATI100-10N 比較
詳細並排比較 EPM3064ATC100-10N 由 Altera 與 EPM3064ATI100-10N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM3064ATC100-10N | EPM3064ATI100-10N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 64 | 64 |
| Logic Array Blocks (LABs) | 2 | 4 |
| Maximum User I/O Pins | 66 | — |
| Usable Gates | 1,250 | 1,250 |
| Pin-to-Pin Delay (tPD) | 10 ns | 10 ns (-10 speed grade) |
| Supply Voltage (VCCINT) | 3.3 V (3.0 V to 3.6 V) | — |
| In-System Programmability | Yes - IEEE Std. 1149.1 JTAG, IEEE Std. 1532 | — |
| Boundary-Scan Test (BST) | Yes - JTAG compliant | — |
| Configuration Memory | Non-volatile EEPROM | — |
| Program/Erase Cycles | 100 minimum | — |
| MultiVolt I/O | Yes - 1.8 V / 2.5 V / 3.3 V / 5 V tolerant | Supports 2.5 V / 3.3 V / 5 V mixed-voltage interfacing |
| 工作溫度 | 0C to +70C (commercial) | -40 C to +85 C (industrial) |
| 封裝 | 100-pin TQFP | 100-pin TQFP (industrial) |
| 安裝類型 | Surface Mount | — |
| RoHS 狀態 | Compliant (lead-free) | RoHS Non-Compliant |
| Programmable Type | — | In-System Programmable (ISP) via IEEE 1149.1 JTAG |
| Technology | — | CMOS EEPROM |
| User I/O | — | 66 |
| Supply Voltage (Core / I/O) | — | 3.3 V |
| Maximum Internal Frequency | — | 227.3 MHz (counter) |
| JTAG (IEEE 1149.1) | — | Yes |
| PCI Compliance | — | PCI Local Bus Specification Revision 2.2 (-4/-5/-6/-7/-10 speed grades) |
| Lead-Free Status | — | Contains Lead |