EPM3064ATC100-7N vs EPM3064ATC-100-10N 比較
詳細並排比較 EPM3064ATC100-7N 由 Altera 與 EPM3064ATC-100-10N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM3064ATC100-7N | EPM3064ATC-100-10N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | 啟用中 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Macrocells | 64 | — |
| Logic Array Blocks (LABs) | 2 | 2 |
| User I/O Pins | 66 | 66 |
| Usable Gates | up to 1,250 | — |
| Propagation Delay (tPD) | 7.5 ns (pin-to-pin, -7 speed grade) | — |
| Maximum Internal Frequency | 166.7 MHz (-7 speed grade) | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V or 2.5 V | — |
| Program Memory Technology | EEPROM (non-volatile) | — |
| In-System Programming | IEEE Std. 1149.1 (JTAG), IEEE Std. 1532 | — |
| 封裝 | TQFP-100 | TQFP-100 |
| 安裝類型 | Surface Mount | Surface Mount |
| 工作溫度 | 0 °C to +70 °C (commercial) | 0C to +70C (commercial) |
| RoHS 狀態 | [DATA_NEEDED: confirmed RoHS status from manufacturer page] | Compliant |
| Macro Cells | — | 64 |
| Usable Gates (min) | — | 600 |
| Usable Gates (typical) | — | 1,250 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Counter Frequency (fCNT) | — | 227.3 MHz |
| Supply Voltage (VCCINT) | — | 3.3 V |
| In-System Programmability | — | Yes (IEEE 1532 / JTAG 1149.1) |
| Programming Interface | — | 4-pin JTAG (TCK/TMS/TDI/TDO) |