EPM3128ATC144-10N vs EPM3128ATC144-5N 比較

詳細並排比較 EPM3128ATC144-10N 由 Intel 與 EPM3128ATC144-5N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Altera
EPM3128ATC144-5N EPM3128ATC144-5N - MAX 3000A 128-Macro 5ns CPLD | Altera

EPM3128ATC144-5N - MAX 3000A 128-Macro 5ns CPLD | Altera

EPM3128ATC144-5N ⚠ 最後購買機會

規格比較

參數 EPM3128ATC144-10N EPM3128ATC144-5N
品牌 Intel Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 啟用中 最後購買
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD - Complex Programmable Logic Device
Macro Cells 128 —
Usable Gates 2,500 (up to 10,000 for full family) 2500
Logic Array Blocks (LABs) 8 —
User I/Os 96 —
Propagation Delay (tPD) 10 ns (speed grade -10) —
Counter Frequency (fCNT) 98 MHz —
Supply Voltage (VCCINT/VCCIO) 3.3 V —
MultiVolt I/O Support 3.3 V / 2.5 V / 1.8 V —
Configuration Memory EEPROM (in-system programmable, non-volatile) —
封裝 144-pin TQFP 144-pin TQFP (20x20 mm)
安裝類型 Surface Mount Surface Mount
工作溫度 0 °C to +70 °C (commercial) 0C to 70C (Commercial)
JTAG (IEEE 1149.1) Yes (BST + pin-locking) —
ISP (IEEE 1532) Yes —
Logic Family — CMOS
Macrocells — 128
User I/O — 96
Pin-to-Pin Logic Delay — 5 ns
Counter Frequency — up to 227.3 MHz
Supply Voltage (Core) — 3.3 V
I/O Logic Levels Supported — 5.0 V / 3.3 V / 2.5 V (MultiVolt)
In-System Programmability — Yes (3.3-V via JTAG)
JTAG Boundary Scan — IEEE Std 1149.1 compliant
RoHS 狀態 — Compliant (lead-free)

資料表與資源

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