EPM3128ATI144-7N vs EPM3128ATC144-7N 比較
詳細並排比較 EPM3128ATI144-7N 由 Altera 與 EPM3128ATC144-7N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM3128ATI144-7N - 128 Macrocell CPLD, 129.9MHz, 3.3V | Altera MAX 3000A
EPM3128ATI144-7N ⚠ 最後購買機會
規格比較
| 參數 | EPM3128ATI144-7N | EPM3128ATC144-7N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | 啟用中 |
| 單價 (USD) | — | $9.25 |
| Family | MAX 3000A | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Logic Capacity | 2.5K gates | — |
| Macrocells | 128 | — |
| Maximum Frequency (fMAX) | 129.9 MHz | — |
| Pin-to-Pin Propagation Delay | 7.5 ns (speed grade -7) | — |
| User I/O Pins | 96 | — |
| Core Supply Voltage (VCCINT) | 3.3 V | 3.3 V |
| I/O Supply Voltage (VCCIO) | 3.3 V / 2.5 V / 1.8 V | 2.5 V / 3.3 V / 5.0 V (MultiVolt) |
| Programmable Logic Technology | CMOS EEPROM | — |
| Programming Interface | JTAG (IEEE Std 1149.1) in-system programmable | — |
| 封裝 | 144-pin TQFP | TQFP-144 (20 x 20 mm, 0.5 mm pitch) |
| Terminal Pitch | 0.5 mm | — |
| JEDEC Package Code | S-PQFP-G144 | — |
| 工作溫度 | -40C to +85C (industrial) | 0 °C to +70 °C (commercial) |
| MultiVolt I/O | Yes (interfaces with 5.0V/3.3V/2.5V/1.8V logic) | — |
| Series | — | MAX 3000A |
| Architecture | — | EEPROM-based, MAX architecture |
| Number of Macrocells | — | 128 |
| Number of Usable Gates | — | Up to 10,000 |
| User I/Os | — | 96 |
| 腳位數 | — | 144 |
| Logic Family | — | CMOS |
| Propagation Delay (tPD) | — | 7.5 ns (pin-to-pin, -7 speed grade) |
| Counter Frequency | — | Up to 227.3 MHz |
| In-System Programmability (ISP) | — | Yes, via JTAG (IEEE 1149.1) |
| PCI Compliance | — | Compatible with PCI Local Bus Specification Rev. 2.2 |
| 安裝類型 | — | Surface Mount (SMD/SMT) |
| RoHS 狀態 | — | Lead-free (-7N suffix indicates Pb-free finish) |