EPM3512AFC256-19 vs EPM3512AFC256-18 比較
詳細並排比較 EPM3512AFC256-19 由 Altera 與 EPM3512AFC256-18 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM3512AFC256-18 - MAX 3000A CPLD, 512 Macrocells, BGA-256 | Altera
EPM3512AFC256-18 Obsolete規格比較
| 參數 | EPM3512AFC256-19 | EPM3512AFC256-18 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 512 | 512 |
| Usable Gates | 10000 | — |
| Logic Array Blocks (LABs) | 16 | 16 |
| Maximum Operating Frequency | 80 MHz | — |
| Pin-to-Pin Delay (tPD) | 7.5 ns | — |
| Speed Grade | -19 | — |
| User I/O Pins | 208 | — |
| 封裝 | 256-ball FineLine BGA (FC) | 256-ball FineLine BGA (FCBGA) |
| Supply Voltage VCCINT | 3.3 V | — |
| I/O Supply Voltage VCCIO | 2.5 V or 3.3 V (5.0 V tolerant inputs) | — |
| Programming Interface | JTAG (IEEE 1149.1) / ISP (IEEE 1532) | — |
| Process Technology | 0.30 µm CMOS EEPROM | — |
| 工作溫度 | -40C to +85C (industrial) | [DATA_NEEDED: industrial/commercial grade] |
| Non-volatile Configuration | Yes (EEPROM-based) | — |
| 安裝類型 | Surface Mount | Surface Mount |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: not specified in retrieved data] |
| Maximum User I/O Pins | — | 212 |
| Pin-to-Pin Delay (tPD1) | — | 18 ns |
| Global Clock Networks | — | 4 |
| VCCINT (Core Supply) | — | 3.0 V to 3.6 V (3.3 V typical) |
| VCCIO (I/O Supply) | — | 2.5 V or 3.3 V (MultiVolt) |
| Programming Technology | — | EEPROM (non-volatile) |
| In-System Programming | — | IEEE Std. 1532 / JTAG (IEEE Std. 1149.1) |
| Ball Pitch | — | 1.0 mm |