EPM3512AFC256-3N vs EPM3512AFC256-5C 比較
詳細並排比較 EPM3512AFC256-3N 由 Altera 與 EPM3512AFC256-5C 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM3512AFC256-5C - MAX 3000A CPLD, 512 Macrocells, 256-BGA | Altera
EPM3512AFC256-5C Obsolete規格比較
| 參數 | EPM3512AFC256-3N | EPM3512AFC256-5C |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | Obsolete |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 512 | 512 |
| Usable Gates | 10,000 | 10,000 |
| Logic Array Blocks (LABs) | 16 | — |
| Maximum Operating Frequency | 116.3 MHz | 95.2 MHz |
| Pin-to-Pin Delay (tPD) | 3.5 ns (speed grade -3) | 5 ns |
| Speed Grade | -3 (slowest in family) | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (MultiVolt) | — |
| 封裝 | 256-ball FineLine BGA (FC-256) | 256-ball FBGA, 17 mm × 17 mm, 1.0 mm pitch |
| 安裝類型 | Surface Mount | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1) / IEEE Std. 1532 ISP | IEEE Std. 1532 / JTAG (4-wire) in-system programmable |
| Configuration Memory | Non-volatile EEPROM | — |
| 工作溫度 | [DATA_NEEDED: operating temperature grade] | 0 °C to +70 °C (commercial, "C" grade) |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Supply Voltage - Core (VCCINT) | — | 3.3 V |
| I/O Voltage (VCCIO) | — | 2.5 V / 3.3 V / 5.0 V (banked MultiVolt I/O) |
| User I/O Pins | — | 212 (max) |
| Technology | — | EEPROM-based macrocell, non-volatile |