EPM3512AQC208-10 vs EPM3256AQC208-10 比較
詳細並排比較 EPM3512AQC208-10 由 Altera 與 EPM3256AQC208-10 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM3256AQC208-10 - MAX 3000A CPLD 256 Macrocells 10ns 208-PQFP | Intel / Altera
EPM3256AQC208-10 Obsolete規格比較
| 參數 | EPM3512AQC208-10 | EPM3256AQC208-10 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 3000A | MAX 3000A |
| Usable Gates | 10,000 | 5,000 |
| Macrocells | 512 | 256 |
| Logic Array Blocks (LABs) | 32 | — |
| User I/Os | 208 | 161 |
| Propagation Delay (tPD) | 7.5 ns | — |
| Maximum Frequency (fCNT) | 116.3 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V | 3.3 V |
| Configuration Memory | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (IEEE Std. 1532) | — |
| JTAG Boundary Scan | Yes (IEEE 1149.1) | — |
| PCI Compliance | PCI Local Bus Spec Rev. 2.2 (-10 speed grade) | — |
| 封裝 | 208-pin PQFP | 208-BFQFP (PQFP, Gull Wing) |
| 工作溫度 | 0C to +70 C (commercial) | 0 °C to +70 °C (Commercial) |
| RoHS 狀態 | [DATA_NEEDED: RoHS status not in verified data] | [DATA_NEEDED: RoHS status] |
| Logic Family | — | CMOS (EEPROM-based) |
| 腳位數 | — | 208 |
| Pin-to-Pin Propagation Delay | — | 10 ns |
| Counter Frequency (max) | — | 227.3 MHz |
| I/O Tolerance | — | MultiVolt 2.5 V / 3.3 V / 5.0 V tolerant |
| Programming Interface | — | IEEE 1149.1 JTAG (ISP) |
| PCI-SIG Compliance | — | Yes (speed grades -4, -5, -6, -7, -10) |
| Global Clock Networks | — | 4 (CLK, CLR, OE, GCLK) |
| 安裝類型 | — | Surface Mount |