EPM3512AQC208-7N vs EPM3512AQI208-7 比較
詳細並排比較 EPM3512AQC208-7N 由 Altera 與 EPM3512AQI208-7 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM3512AQC208-7N | EPM3512AQI208-7 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | NRND |
| Family | MAX 3000A | MAX 3000A |
| Logic Capacity | 512 macrocells, 10,000 usable gates | — |
| Logic Array Blocks (LABs) | 32 | 16 |
| Macrocells per LAB | 16 | — |
| User I/Os | 172 | — |
| Propagation Delay (tPD) | 7.5 ns | — |
| Maximum Frequency (fCNT) | 116.3 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V (3.0 V to 3.6 V) | — |
| I/O Bank Count | 4 (MultiVolt) | — |
| Supported I/O Standards | 1.8 V / 2.5 V / 3.3 V LVTTL/LVCMOS | — |
| Process Technology | 0.30 µm CMOS EEPROM | — |
| Configuration | Non-volatile EEPROM, in-system programmable (ISP) | — |
| JTAG Interface | IEEE 1149.1 BST + IEEE 1532 ISP | — |
| 封裝 | 208-Pin PQFP / FQFP-208 (Plastic Quad Flat Pack, gull-wing) | 208-pin PQFP |
| 工作溫度 | 0 °C to +70 °C (commercial) | -40C to +85C (industrial) |
| RoHS 狀態 | Compliant | — |
| Speed Grade | -7 | -7 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 10,000 |
| Macro Cells | — | 512 |
| Maximum Operating Frequency | — | 116.3 MHz |
| Pin-to-Pin Delay (tPD) | — | [DATA_NEEDED: tPD in ns] |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 2.5 V / 3.3 V / 5.0 V |
| Programmability | — | Non-volatile, in-system programmable (IEEE Std. 1532) |
| JTAG Support | — | Yes (IEEE 1149.1 boundary scan + ISP) |
| User I/O Pins | — | [DATA_NEEDED: user I/O count for PQFP-208] |
| 安裝類型 | — | Surface Mount |
| Lead-Free / RoHS | — | Compliant per Altera product page |