EPM5016DC-20 vs EPM5064JC-1 比較
詳細並排比較 EPM5016DC-20 由 Altera 與 EPM5064JC-1 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5016DC-20 | EPM5064JC-1 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (UV-Erasable Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 16 | — |
| Product Terms | 160 | — |
| Dedicated Inputs | 7 | [DATA_NEEDED: dedicated input count] |
| I/O Pins | 8 | — |
| Propagation Delay (tPD) | 20 ns | — |
| 最大時脈頻率 | 62.5 MHz | — |
| Maximum Supply Voltage | 5.25 V | — |
| Nominal Supply Voltage | 5.0 V | — |
| Process Technology | CMOS, UV-erasable | 0.8 µm CMOS |
| Architecture | PAL-type macrocell with Programmable Interconnect Array (PIA) | — |
| Package Type | 20-pin Ceramic DIP (Cerdip) with UV window | — |
| Package Suffix Code | DC = Ceramic DIP, Commercial | — |
| Speed Grade | -20 = 20 ns tPD | — |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | 0 °C to +70 °C (commercial, -JC suffix) |
| Programming Method | UV erase + EPROM-style programming via Altera programming hardware | Altera Logic Programmer + MasterBlaster/ByteBlasterMV |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance] | Non-compliant (windowed ceramic, contains Pb in glass frit) |
| Macro Cells | — | 64 |
| Usable Gates | — | 1250 (typical) |
| Logic Elements | — | 128 (Logic Array Blocks) |
| Maximum Operating Frequency | — | 33.3 MHz (fCNT) |
| Pin-to-Pin Delay (tPD) | — | [DATA_NEEDED: tPD typical/max in ns] |
| Supply Voltage (VCC) | — | 5 V nominal (4.75 V – 5.25 V) |
| Programmable Pins | — | 36 (typical I/O, 44-pin PLCC) |
| 封裝 | — | 44-pin PLCC (J-lead, windowed ceramic) |
| 安裝類型 | — | Surface Mount (PLCC socket recommended) |
| Erasure Method | — | UV-erasable through quartz window |
| JTAG Boundary Scan | — | Not supported (classic MAX architecture) |
| Military/Avionics SMD | — | 5962-01-417-3750 (QML variant: EPM5064JM/883) |