EPM5032PC-15 vs EPM5032DC-15 比較
詳細並排比較 EPM5032PC-15 由 Altera 與 EPM5032DC-15 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM5032DC-15 - 600-Gate, 32-Macrocell UV PLD | Altera MAX 5000 | DIP-28
EPM5032DC-15 Obsolete規格比較
| 參數 | EPM5032PC-15 | EPM5032DC-15 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Family | MAX 5000 | — |
| Device Type | EPLD (Erasable PLD) | UV-erasable EPLD (PAL-type CMOS) |
| Macro Cells | 32 | — |
| Usable Gates | 600 | 600 |
| Logic Elements / LABs | 1 LAB (4 macrocells per group) | — |
| Propagation Delay (tPD) | 15 ns | 15 ns |
| Maximum Internal Frequency | 76.9 MHz (some sources list 83.3 MHz) | — |
| Operating Voltage (VCC) | 5 V (typ.) | — |
| Technology Node | 0.8 micron CMOS | — |
| Configuration Memory | UV-Erasable EPROM | — |
| Dedicated Inputs | 7 | — |
| Bidirectional I/O Pins | 16 | — |
| Total Array Inputs | 24 | — |
| 封裝 | 28-pin PDIP (PC suffix = windowed CerDIP) | CERDIP-28 (windowed, through-hole) |
| Pin/Package Suffix | PC = Windowed Ceramic DIP | — |
| Speed Grade | 15 (15 ns tPD) | — |
| 工作溫度 | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Programming Tool | Altera Logic Programmer + MAX+plus II | — |
| RoHS 狀態 | Non-compliant (CerDIP window, contains Be) | [DATA_NEEDED: RoHS status] |
| Lead-Free | No | unknown |
| 安裝類型 | Through-Hole (DIP) | Through-Hole (DIP) |
| Family | — | MAX 5000 |
| Macrocells | — | 32 |
| Maximum Toggle Frequency (fMAX) | — | 83.3 MHz |
| Supply Voltage (VCC) | — | 5 V (nominal) |
| Logic Family | — | CMOS, TTL-compatible I/O |
| Programmable Pins | — | 16 bidirectional I/O + 4 dedicated input = 20 |
| Total Package Pins | — | 28 |
| Erasure Method | — | UV light through ceramic quartz window |
| Process Technology | — | CMOS |