EPM5064JC-2 vs EPM5064JC1 比較
詳細並排比較 EPM5064JC-2 由 Altera 與 EPM5064JC1 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5064JC-2 | EPM5064JC1 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Macrocells | 64 | 64 |
| Logic Array Blocks (LABs) | 4 | 4 |
| Propagation Delay (tPD) | 45 ns | — |
| Maximum Clock Frequency (fMAX) | 50 MHz | — |
| Usable Gates | 1250 | 1.25K |
| Dedicated Inputs | 7 | 7 |
| I/O Pins | 28 | 28 |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Technology | CMOS, UV-erasable EPROM | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | — |
| Programming Method | UV-erase + EPROM programmer (not ISP) | — |
| 封裝 | 28-pin CLCC (J-lead, ceramic, windowed) | 44-pin PLCC (J-Lead) |
| 工作溫度 | [DATA_NEEDED: commercial or industrial grade] | — |
| Compliance | RoHS status unknown (ceramic/J-lead windowed part, legacy product) | — |
| Device Type | — | CPLD / EPLD (Erasable PLD) |
| Maximum Operating Frequency (fCNT) | — | 62.5 MHz |
| External Clock Input (max) | — | 50 MHz |
| Total Inputs | — | 36 (28 I/O + 7 dedicated + 1 clock) |
| Operating Voltage (VCC) | — | 5 V |
| Program Type | — | EPROM (one-time programmable, UV-erasable) |
| Process Technology | — | CMOS |
| Operating Temperature (JC suffix) | — | 0°C to +70°C (commercial) |
| Supply Current (ICC) | — | [DATA_NEEDED: ICC maximum] |
| RoHS 狀態 | — | unknown |
| Lead-Free Status | — | unknown |