EPM5064JC1 vs EPM5064LC 比較
詳細並排比較 EPM5064JC1 由 Altera 與 EPM5064LC 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5064JC1 | EPM5064LC |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | CPLD / EPLD (Erasable PLD) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 64 | — |
| Logic Array Blocks (LABs) | 4 | 4 |
| Usable Gates | 1.25K | 1.25K |
| Maximum Operating Frequency (fCNT) | 62.5 MHz | — |
| External Clock Input (max) | 50 MHz | — |
| I/O Pins | 28 | 28 bidirectional + 4 dedicated input |
| Dedicated Inputs | 7 | — |
| Total Inputs | 36 (28 I/O + 7 dedicated + 1 clock) | 36 (7 dedicated + 29 I/O) |
| Operating Voltage (VCC) | 5 V | — |
| Program Type | EPROM (one-time programmable, UV-erasable) | — |
| Process Technology | CMOS | CMOS EPROM |
| 封裝 | 44-pin PLCC (J-Lead) | PLCC-44 (LCC-44, J-lead) |
| Operating Temperature (JC suffix) | 0°C to +70°C (commercial) | — |
| Supply Current (ICC) | [DATA_NEEDED: ICC maximum] | — |
| RoHS 狀態 | unknown | [DATA_NEEDED: RoHS status - pre-RoHS legacy part, likely non_compliant] |
| Lead-Free Status | unknown | — |
| Programming Type | — | OTP (One-Time-Programmable, UV-erasable EPROM) |
| Macro Cells | — | 64 |
| Propagation Delay (tPD) | — | 55 ns |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| 工作溫度 | — | 0C to +70C (Commercial) |
| 安裝類型 | — | Surface Mount |
| Lead Free | — | [DATA_NEEDED: lead-free status] |